Sheng-Liang Pan has uploaded this change for review.

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mb/google/volteer/var/voxel: Update DPTF parameters

change TCC offset to 10C.

BUG=b:174547185
TEST=emerge-volteer coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
---
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48264/1

diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 9c4aa47..c60528c 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/tigerlake
 	register "DdiPort1Hpd" = "0"
 	register "DdiPort2Hpd" = "0"
-	register "tcc_offset" = "5"     # TCC of 95
+	register "tcc_offset" = "10"     # TCC of 90
 
 	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
 		.tdp_pl1_override = 18,

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