HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33673
Change subject: src: Move 'static' is at beginning of declaration ......................................................................
src: Move 'static' is at beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/1
diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aec..c56b537 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0
-const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..a1ba310 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ } }
-const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13};
static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ u32 emrs1;
/* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 32618e8..8ca6ec1 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ 5200 };
- const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ };
/* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ } };
- const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..50da155 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -173,7 +173,7 @@ * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -182,7 +182,7 @@ .TPMA_NV_POLICY_DELETE = 1, };
-const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -193,7 +193,7 @@ * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..f68ab0a4 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ea..e1df91f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -116,7 +116,7 @@ * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" }, diff --git a/src/soc/intel/fsp_broadwell_de/gpio.c b/src/soc/intel/fsp_broadwell_de/gpio.c index 41100e9..01c4d9e 100644 --- a/src/soc/intel/fsp_broadwell_de/gpio.c +++ b/src/soc/intel/fsp_broadwell_de/gpio.c @@ -24,7 +24,7 @@ #include <soc/gpio.h>
/* Use a wrapper for register addresses for different banks. */ -const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = { +static const struct gpio_config_regs regs[GPIO_NUM_BANKS] = { [0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL, .level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN, .blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT },
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' is at beginning of declaration ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/33673/1/src/northbridge/intel/x4x/dq_dqs.c File src/northbridge/intel/x4x/dq_dqs.c:
https://review.coreboot.org/#/c/33673/1/src/northbridge/intel/x4x/dq_dqs.c@5... PS1, Line 543: static const u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/#/c/33673/1/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/#/c/33673/1/src/security/vboot/vboot_crtm.c@32 PS1, Line 32: static const char *fmap_cbfs_names[] = { static const char * array should probably be static const char * const
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' is at beginning of declaration ......................................................................
Patch Set 1: Code-Review+1
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33673
to look at the new patch set (#2).
Change subject: src: Move 'static' is at beginning of declaration ......................................................................
src: Move 'static' is at beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' is at beginning of declaration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33673/2/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/#/c/33673/2/src/security/vboot/vboot_crtm.c@32 PS2, Line 32: static const char *fmap_cbfs_names[] = { static const char * array should probably be static const char * const
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33673
to look at the new patch set (#3).
Change subject: src: Move 'static' at beginning of declaration ......................................................................
src: Move 'static' at beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/3
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33673
to look at the new patch set (#4).
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
src: Move 'static' to the beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/33673/5/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/#/c/33673/5/src/security/vboot/vboot_crtm.c@32 PS5, Line 32: static const char *fmap_cbfs_names[] = { static const char * array should probably be static const char * const
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33673/7/src/security/vboot/vboot_cr... File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/c/coreboot/+/33673/7/src/security/vboot/vboot_cr... PS7, Line 32: static const char *fmap_cbfs_names[] = { static const char * array should probably be static const char * const
Hello Patrick Rudolph, Aaron Durbin, Angel Pons, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33673
to look at the new patch set (#8).
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
src: Move 'static' to the beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c 6 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33673/8/src/security/vboot/vboot_cr... File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/c/coreboot/+/33673/8/src/security/vboot/vboot_cr... PS8, Line 32: static const char *fmap_cbfs_names[] = { static const char * array should probably be static const char * const
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33673 )
Change subject: src: Move 'static' to the beginning of declaration ......................................................................
src: Move 'static' to the beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c 6 files changed, 12 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aec..c56b537 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0
-const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..d48601d 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ } }
-const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13};
static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ u32 emrs1;
/* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..dd48d8a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ 5200 };
- const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ };
/* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ } };
- const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 2fbb30b..0afd00d 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -133,7 +133,7 @@ * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -142,7 +142,7 @@ .TPMA_NV_POLICY_DELETE = 1, };
-const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -153,7 +153,7 @@ * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..f68ab0a4 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aa..8556790 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -43,7 +43,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -115,7 +115,7 @@ * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" },
-
Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)
-
HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)