[M] Change in coreboot[main]: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Tarun, Tim Crawford.

Subrata Banik has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82733?usp=email )

Change subject: soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/82733/comment/e93de523_8ac73740?usp... :
PS1, Line 14: 
looks like you are trying to change the existing system behavior where we prefer to read SPD via SMBUS. Rather you are trying to pass the SPD static data for DDR5 as well.

technically, what you are trying is yet another way to fill the SPD but that doesn't mean we shall drop the SMBUS read (which would allow anyone to alter the DIMM w/o really need to bother about passing SPD hex data for each DIMM configuration.

hence, my suggestion is to add some Kconfig kind if possible to keep SPD fill vis SMBUS in parallel to fill SPD using static hex data w/o dropping the previous one.