Change in coreboot[master]: soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N

[Krishna P Bhat D (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Reka Norman, Usha P, Ronak Kanabar, Patrick Rudolph.
Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61127 )

Change subject: soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
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Patch Set 6:

(2 comments)

File src/soc/intel/alderlake/acpi/scs.asl:

https://review.coreboot.org/c/coreboot/+/61127/comment/c4f78f49_9a6ad16b 
PS6, Line 21: Name (TEMP, 0)
> I don't understand what this is used for. […]

This variable is used to do an additional read to the eMMC controller.

https://review.coreboot.org/c/coreboot/+/61127/comment/a76c27a5_7220b28f 
PS6, Line 58: PMCR = PMCR | 0x0003
            : 			TEMP = PMCR
> Did you possibly mean this? […]

This is an additional config read to the eMMC controller after the controller has been power gated (put to D3). It is not being used to write back into any registers.
https://review.coreboot.org/c/coreboot/+/23312