Change in coreboot[master]: mb/apple: Add iMac13,1 (21.5-inch, Late 2012) - coreboot-gerrit

13 Feb 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38883 )
Change subject: mb/apple: Add iMac13,1 (21.5-inch, Late 2012)
......................................................................
mb/apple: Add iMac13,1 (21.5-inch, Late 2012)
This piece of aluminium has a 820-3302A logic board.
DANGER: IN ORDER TO ACCESS THE FLASH CHIP, IT IS NECESSARY TO REMOVE THE
LCD ASSEMBLY, UNDER WHICH THERE IS THE POWER SUPPLY AS WELL. THE POWER
SUPPLY OPERATES WITH MAINS VOLTAGE, AND CONTAINS CAPACITORS WHICH MAY
REMAIN CHARGED EVEN AFTER THE UNIT IS UNPLUGGED. MOREOVER, AS THE POWER
SUPPLY USES AN ACTIVE PFC (POWER FACTOR CORRECTION) CIRCUIT, VOLTAGES IN
EXCESS OF 400 VOLTS ARE PRESENT ACROSS THE PRIMARY FILTER CAPACITORS
UNDER NORMAL OPERATION IRRESPECTIVE OF THE MAINS INPUT VOLTAGE. THUS, IT
IS NECESSARY TO VERIFY NO SUCH VOLTAGES ARE PRESENT BEFORE SERVICING THE
UNIT. FAILURE TO DO SO CAN RESULT IN POTENTIALLY LETHAL ELECTRIC SHOCK.
UNLESS YOU CLEARLY UNDERSTAND THE ASSOCIATED RISKS, DO NOT PROCEED!
(note: there is no electrical hazard associated to reviewing this change)
Not working:
- External monitors. The Nvidia GPU starts up fine, the display appears
  on Xorg.0.log, but DisplayPort signals do not reach the display. It is
  very likely due to Cactus Ridge being a completely undocumented prick.
- Cactus Ridge, the Thunderbolt controller. There isn't even a damn
  datasheet for this thing, so it's a literal black magic box. I mean,
  the package of this thing is black and square... Anyway, cursed sand.
- Fan is pretending to be a leaf blower. Yes, it is a Delta fan.
- No support at all for the SMC. It probably controls the leaf blower.
- Using a chip clip. The hardware is not designed for such atrocities.
Untested:
- Front access door. It is made out of LCD. It also has a backlight.
- Broadcom BCM4331 PCIe Wi-Fi card. Probably works fine.
- Gumstick (Apple's SSD connector). Donations are welcome.
- Webcam. Probably works fine, especially if removing the tape on it.
- S3 resume. Probably needs correcting DRAM_RESET_GATE_GPIO.
- Audio. It uses the Cirrrrrus CS4206, which had issues with headphones.
- Vertical orientation. The board has been tested bare, on a table.
Tested and working:
- Ivy Bridge i7-3770S
- A pair of 4GB DDR3 SO-DIMM sticks with native raminit
- Broadcom BCM57765 (Caesar IV) Ethernet NIC
- Some USB ports
- SATA port with a SSD
- Booting enough to use SSH via Ethernet
- Flashing internally with coreboot
- Running off a random ATX PSU's 12V rail
- Toggling the debug LED wired to GPIO35
Change-Id: If5063254b3eb5cda2a6d3396669700b405a51081
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
A src/mainboard/apple/imac13_1/Kconfig
A src/mainboard/apple/imac13_1/Kconfig.name
A src/mainboard/apple/imac13_1/Makefile.inc
A src/mainboard/apple/imac13_1/acpi/ec.asl
A src/mainboard/apple/imac13_1/acpi/platform.asl
A src/mainboard/apple/imac13_1/acpi/superio.asl
A src/mainboard/apple/imac13_1/acpi_tables.c
A src/mainboard/apple/imac13_1/board_info.txt
A src/mainboard/apple/imac13_1/devicetree.cb
A src/mainboard/apple/imac13_1/dsdt.asl
A src/mainboard/apple/imac13_1/early_init.c
A src/mainboard/apple/imac13_1/gpio.c
A src/mainboard/apple/imac13_1/hda_verb.c
13 files changed, 559 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38883/1

diff --git a/src/mainboard/apple/imac13_1/Kconfig b/src/mainboard/apple/imac13_1/Kconfig
new file mode 100644
index 0000000..6eda6c3
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/Kconfig
@@ -0,0 +1,48 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_APPLE_IMAC13_1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_C216
+	select USE_NATIVE_RAMINIT
+	select NO_UART_ON_SUPERIO
+
+config MAINBOARD_DIR
+	string
+	default apple/imac13_1
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "iMac13,1"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+	int
+	default 60
+
+config MAX_CPUS
+	int
+	default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	int
+	default 2
+endif
diff --git a/src/mainboard/apple/imac13_1/Kconfig.name b/src/mainboard/apple/imac13_1/Kconfig.name
new file mode 100644
index 0000000..7115f46
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_APPLE_IMAC13_1
+	bool "iMac13,1 (21.5-inch, Late 2012) (820-3302A)"
diff --git a/src/mainboard/apple/imac13_1/Makefile.inc b/src/mainboard/apple/imac13_1/Makefile.inc
new file mode 100644
index 0000000..7df4de7
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += gpio.c
+romstage-y  += gpio.c
+
+bootblock-y += early_init.c
+romstage-y  += early_init.c
diff --git a/src/mainboard/apple/imac13_1/acpi/ec.asl b/src/mainboard/apple/imac13_1/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/acpi/ec.asl
diff --git a/src/mainboard/apple/imac13_1/acpi/platform.asl b/src/mainboard/apple/imac13_1/acpi/platform.asl
new file mode 100644
index 0000000..9975095
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/acpi/platform.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS enters a sleep state.
+ * The sleep state number is passed in Arg0.
+ */
+Method(_PTS,1)
+{
+}
+
+/*
+ * The _WAK method is called on system wakeup.
+ */
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/apple/imac13_1/acpi/superio.asl b/src/mainboard/apple/imac13_1/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/acpi/superio.asl
diff --git a/src/mainboard/apple/imac13_1/acpi_tables.c b/src/mainboard/apple/imac13_1/acpi_tables.c
new file mode 100644
index 0000000..ca35db2
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/acpi_tables.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	gnvs->tcrt = 100;
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/imac13_1/board_info.txt b/src/mainboard/apple/imac13_1/board_info.txt
new file mode 100644
index 0000000..62bf64d
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+ROM protocol: SPI
+Flashrom support: y
+ROM package: SOIC-8
+ROM socketed: n
+Release year: 2012
diff --git a/src/mainboard/apple/imac13_1/devicetree.cb b/src/mainboard/apple/imac13_1/devicetree.cb
new file mode 100644
index 0000000..cb6e2f8
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/devicetree.cb
@@ -0,0 +1,79 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x106b 0x0107 inherit
+
+		device pci 00.0 on  end		# Host bridge
+		device pci 01.0 on  end		# PEG
+		device pci 02.0 off end		# iGPU
+
+		chip southbridge/intel/bd82x6x	# Intel Z77 PCH
+
+			register "c2_latency" = "0x0065"
+			register "gen1_dec" = "0x000c0681"
+			register "gen2_dec" = "0x000c1641"
+			register "gen3_dec" = "0x001c0301"
+			register "gen4_dec" = "0x00fc0701"
+
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3"
+			register "spi_lvscc" = "0x0"
+			register "spi_uvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x08040201"
+			register "xhci_switchable_ports"    = "0xf"
+
+			device pci 14.0 on  end		# xHCI
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 16.2 off end		# ME IDE-R
+			device pci 16.3 off end		# ME KT
+			device pci 19.0 off end		# Intel GbE
+			device pci 1a.0 on  end		# USB2 EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+
+			device pci 1c.0 on  end		# RP #1: Gumstick? (x2)
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 on  end		# RP #3: BCM57765 Caesar IV NIC (x1)
+			device pci 1c.3 on  end		# RP #4: Cactus Ridge (x4)
+			device pci 1c.4 on  end		# RP #5
+			device pci 1c.5 off end		# RP #6
+			device pci 1c.6 off end		# RP #7
+			device pci 1c.7 off end		# RP #8
+
+			device pci 1d.0 on  end		# USB2 EHCI #1
+			device pci 1e.0 off end		# PCI bridge
+			device pci 1f.0 on  end		# LPC bridge
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (IDE)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/apple/imac13_1/dsdt.asl b/src/mainboard/apple/imac13_1/dsdt.asl
new file mode 100644
index 0000000..790de6e
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/dsdt.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI 2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	/* OEM revision */
+)
+{
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (_SB.PCI0)
+	{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/apple/imac13_1/early_init.c b/src/mainboard/apple/imac13_1/early_init.c
new file mode 100644
index 0000000..447adf8
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/early_init.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0  },
+	{ 1, 0, 1  },
+	{ 1, 0, 2  },
+	{ 1, 0, 3  },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/apple/imac13_1/gpio.c b/src/mainboard/apple/imac13_1/gpio.c
new file mode 100644
index 0000000..dc4d585
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/gpio.c
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio23 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio11 = GPIO_RESET_RSMRST,
+	.gpio15 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio3 = GPIO_INVERT,
+	.gpio4 = GPIO_INVERT,
+	.gpio5 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,	/* Wired to 3rd diagnostic LED. */
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio47 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,	/* Default to OFF. Can be turned on later. */
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/apple/imac13_1/hda_verb.c b/src/mainboard/apple/imac13_1/hda_verb.c
new file mode 100644
index 0000000..3a24c07
--- /dev/null
+++ b/src/mainboard/apple/imac13_1/hda_verb.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Angel Pons th3fanbus@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10134206,	/* Codec Vendor / Device ID: Cirrus CS4206 */
+	0x106b5a00,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(0, 0x106b5a00),
+	AZALIA_PIN_CFG(0, 0x09, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0a, 0x002b4020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x90100112),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0e, 0x90a60100),
+	AZALIA_PIN_CFG(0, 0x0f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x10, 0x004be030),
+	AZALIA_PIN_CFG(0, 0x12, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x15, 0x400000f0),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If5063254b3eb5cda2a6d3396669700b405a51081
Gerrit-Change-Number: 38883
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-MessageType: newchange



    