[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75619?usp=email )

Change subject: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
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soc/amd/stoneyridge/northbridge: reserve PCI config IO ports

This makes sure that the resource allocator won't use those ports for
anything else.

Signed-off-by: Felix Held 
Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/stoneyridge/northbridge.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Raul Rangel: Looks good to me, approved
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 75fdfa4..452a7bb 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -334,6 +334,8 @@

pci_domain_read_resources(dev);

+	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+
    /* 0x0 -> 0x9ffff */
    ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);