[S] Change in coreboot[master]: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74158 )

Change subject: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error
......................................................................

soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error

This patch prevents the Three Strike Counter from incrementing,
which would help to disable Machine Check Catastrophic error.
It will provide more opportunity to collect more useful CPU
traces for debugging.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik 
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74158/1

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index bfa4818..3f0ee67 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -569,3 +569,12 @@
 {
    return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ;
 }
+
+void disable_three_strike_error(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PREFETCH_CTL);
+	msr.lo = msr.lo | DISABLE_CPU_ERROR;
+	wrmsr(MSR_PREFETCH_CTL, msr);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index c72e1ea..a33a722 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -222,4 +222,11 @@
  * Returns true if Key Locker feature is supported otherwise false.
  */
 bool is_keylocker_supported(void);
+
+/*
+ * This function prevents the Three Strike Counter from incrementing,
+ * it will help to collect more useful CPU traces for debugging.
+ */
+void disable_three_strike_error(void);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index d4d8732..9f95e9f 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -35,6 +35,7 @@
 #define MSR_PREFETCH_CTL	0x1a4
 #define  PREFETCH_L1_DISABLE	(1 << 0)
 #define  PREFETCH_L2_DISABLE	(1 << 2)
+#define   DISABLE_CPU_ERROR		(1 << 11)
 #define MSR_MISC_PWR_MGMT	0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define  MISC_PWR_MGMT_ISST_EN		(1 << 6)