Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52088 )

Change subject: mb/google/brya: Enable south XHCI ports 1 and 2
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mb/google/brya: Enable south XHCI ports 1 and 2

FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.

BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.

Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) 
Reviewed-by: EricR Lai 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 3155d04..d7e2522 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -39,6 +39,12 @@
    register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
+	# TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081
+	# uses port enable for south XHCI ports to determine if TCSS
+	# ports should be enabled. Until FSP is fixed, enable south
+	# XHCI ports 1 and 2.
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
    register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

register "SerialIoI2cMode" = "{