huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: support DDR frequency 3600Mbps
DDR frequency fix at 3600Mbps
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform Signed-off-by: Huayang Duan huayang.duan@mediatek.com
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,677 insertions(+), 262 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/1
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 09bec01..90b17c4 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -20,6 +20,8 @@ #include <soc/dramc_register.h> #include <soc/infracfg.h>
+extern u32 freqTbl[LP4X_DDRFREQ_MAX]; + struct reg_init_value { u32 *addr; u32 value; @@ -1084,15 +1086,1223 @@ {&ch[1].ao.mrs, 0x00000dd8}, };
-void dramc_init(void) -{ - for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++) - write32(dramc_init_sequence[i].addr, - dramc_init_sequence[i].value); +struct reg_init_value dramc_init_sequence_3600[] = { + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x1022a04c, 0x20712000}, + {(u32 *)0x1023204c, 0x20712000}, + {(u32 *)0x1022a024, 0x00100480}, + {(u32 *)0x10232024, 0x00100480}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x10228308, 0x00000003}, + {(u32 *)0x10230308, 0x00000003}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x10228284, 0x00000101}, + {(u32 *)0x10228284, 0x00000101}, + {(u32 *)0x1022829c, 0x38010000}, + {(u32 *)0x10228278, 0x00000000}, + {(u32 *)0x1022827c, 0x00000000}, + {(u32 *)0x10228274, 0x00000000}, + {(u32 *)0x1022828c, 0x006003bf}, + {(u32 *)0x10228294, 0x333f3f00}, + {(u32 *)0x10228d84, 0x0000001f}, + {(u32 *)0x10228c1c, 0x00000010}, + {(u32 *)0x10228c9c, 0x00000000}, + {(u32 *)0x10228d90, 0xe57800ff}, + {(u32 *)0x10228d98, 0xe57800ff}, + {(u32 *)0x10228db8, 0x00000000}, + {(u32 *)0x10228dd0, 0x00000000}, + {(u32 *)0x102281a0, 0x00000000}, + {(u32 *)0x102280a0, 0x00000000}, + {(u32 *)0x10228120, 0x00000000}, + {(u32 *)0x102280bc, 0x10000000}, + {(u32 *)0x1022813c, 0x10000000}, + {(u32 *)0x102281c0, 0x00000000}, + {(u32 *)0x102285f0, 0x10000022}, + {(u32 *)0x10228670, 0x10000022}, + {(u32 *)0x102285f0, 0x10000222}, + {(u32 *)0x10228670, 0x10000222}, + {(u32 *)0x10228608, 0x20000000}, + {(u32 *)0x10228808, 0x20000000}, + {(u32 *)0x10228c14, 0x0030000e}, + {(u32 *)0x10228604, 0x00020002}, + {(u32 *)0x10228608, 0xb0800000}, + {(u32 *)0x10228804, 0x00020002}, + {(u32 *)0x10228808, 0xb0800000}, + {(u32 *)0x10228688, 0x20000000}, + {(u32 *)0x10228888, 0x20000000}, + {(u32 *)0x10228c94, 0x0030000e}, + {(u32 *)0x10228684, 0x00020002}, + {(u32 *)0x10228688, 0xb0800000}, + {(u32 *)0x10228884, 0x00020002}, + {(u32 *)0x10228888, 0xb0800000}, + {(u32 *)0x102285f0, 0x00000222}, + {(u32 *)0x10228670, 0x00000222}, + {(u32 *)0x102280bc, 0x10000001}, + {(u32 *)0x10228e1c, 0x001f1f00}, + {(u32 *)0x10228f1c, 0x001f1f00}, + {(u32 *)0x102280a8, 0x00001010}, + {(u32 *)0x102280ac, 0x00110e10}, + {(u32 *)0x102280b0, 0x010310c0}, + {(u32 *)0x102280ac, 0x02110e00}, + {(u32 *)0x1022813c, 0x10000001}, + {(u32 *)0x10228e6c, 0x001f1f00}, + {(u32 *)0x10228f6c, 0x001f1f00}, + {(u32 *)0x10228128, 0x00001010}, + {(u32 *)0x1022812c, 0x00110e10}, + {(u32 *)0x10228130, 0x010310c0}, + {(u32 *)0x1022812c, 0x02110e00}, + {(u32 *)0x102281a4, 0x0000008c}, + {(u32 *)0x102281b0, 0x00020000}, + {(u32 *)0x10228008, 0x00000011}, + {(u32 *)0x102280a4, 0x00000008}, + {(u32 *)0x10228124, 0x00000008}, + {(u32 *)0x10228da0, 0x00040000}, + {(u32 *)0x10228da4, 0x00000000}, + {(u32 *)0x10228dac, 0x00000000}, + {(u32 *)0x10228da8, 0x00040000}, + {(u32 *)0x1022800c, 0x000c0000}, + {(u32 *)0x10228d80, 0x00000003}, + {(u32 *)0x10228184, 0x00200000}, + {(u32 *)0x102280a4, 0x0000040e}, + {(u32 *)0x10228124, 0x0000040e}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x10228d34, 0x00666009}, + {(u32 *)0x10230d34, 0x00666009}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x10228c34, 0xc0778608}, + {(u32 *)0x10228cb4, 0xc0778608}, + {(u32 *)0x10228d14, 0x00000000}, + {(u32 *)0x10228d00, 0x00104010}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x10228d18, 0x000000c0}, + {(u32 *)0x10230d18, 0x00000040}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x10228c18, 0x00000040}, + {(u32 *)0x10228c98, 0x00000040}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x10228270, 0x00050909}, + {(u32 *)0x10230270, 0x00090909}, + {(u32 *)0x10228d38, 0x00000004}, + {(u32 *)0x10230d38, 0x00000001}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x10228c38, 0x00000001}, + {(u32 *)0x10228cb8, 0x00000001}, + {(u32 *)0x10228004, 0x00000000}, + {(u32 *)0x10228284, 0x0000000f}, + {(u32 *)0x100010b4, 0x00000000},
- for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) { - write32(dramc_mode_reg_init_sequence[i].addr, - dramc_mode_reg_init_sequence[i].value); - udelay(2); + //ddr_phy_reserved_rg_setting line + {(u32 *)0x10228d18, 0x000607c0}, + {(u32 *)0x10230d18, 0x000607c0}, + {(u32 *)0x10228d38, 0x0004e104}, + {(u32 *)0x10228c18, 0x00060740}, + {(u32 *)0x10228c38, 0x00022401}, + {(u32 *)0x10228c98, 0x00060740}, + {(u32 *)0x10228cb8, 0x00022401}, + {(u32 *)0x10230d38, 0x0004e101}, + {(u32 *)0x10230c18, 0x00060740}, + {(u32 *)0x10230c38, 0x00022401}, + {(u32 *)0x10230c98, 0x00060740}, + {(u32 *)0x10230cb8, 0x00022401}, + //ddr_phy_pll_setting + {(u32 *)0x10228d90, 0xe5780000}, + {(u32 *)0x10228d98, 0xe5780000}, + {(u32 *)0x10228270, 0x00050909}, + {(u32 *)0x10228308, 0x00000003}, + {(u32 *)0x10228d00, 0x00144010}, + {(u32 *)0x1022a210, 0x00000000}, + {(u32 *)0x10228d34, 0x00698619}, + {(u32 *)0x10228d38, 0x0004e104}, + {(u32 *)0x10228d18, 0x000607c0}, + {(u32 *)0x102280b4, 0x00000055}, + {(u32 *)0x10228134, 0x00000055}, + {(u32 *)0x102281b4, 0x00000055}, + {(u32 *)0x102281a0, 0x00200000}, + {(u32 *)0x10228284, 0x0000000f}, + {(u32 *)0x10228c18, 0x00060740}, + {(u32 *)0x10228c98, 0x00060740}, + {(u32 *)0x10228d18, 0x000607c0}, + {(u32 *)0x1022800c, 0x000c0000}, + {(u32 *)0x10228000, 0x00000000}, + {(u32 *)0x10228004, 0x00000000}, + {(u32 *)0x10228188, 0x00000000}, + {(u32 *)0x10228088, 0x00000000}, + {(u32 *)0x10228108, 0x00000000}, + {(u32 *)0x10228088, 0x880aec00}, + {(u32 *)0x10228108, 0x880aec00}, + {(u32 *)0x10228188, 0x880bac00}, + {(u32 *)0x10228180, 0x00000000}, + {(u32 *)0x10228080, 0x00000000}, + {(u32 *)0x10228100, 0x00000000}, + {(u32 *)0x10228da0, 0x00040000}, + {(u32 *)0x10228da8, 0x00040000}, + {(u32 *)0x10228d94, 0x8a000002}, + {(u32 *)0x10228d9c, 0x8a000002}, + {(u32 *)0x10228180, 0x00000002}, + {(u32 *)0x10228080, 0x00000002}, + {(u32 *)0x10228100, 0x00000002}, + {(u32 *)0x10228184, 0x00200000}, + {(u32 *)0x10228084, 0x00000000}, + {(u32 *)0x10228104, 0x00000000}, + {(u32 *)0x10228c18, 0x02460740}, + {(u32 *)0x10228c98, 0x02460740}, + {(u32 *)0x10228d18, 0x024607c0}, + {(u32 *)0x10228180, 0x0000000a}, + {(u32 *)0x10228080, 0x0000000a}, + {(u32 *)0x10228100, 0x0000000a}, + {(u32 *)0x10228000, 0x80000000}, + {(u32 *)0x10228004, 0x80000000}, + {(u32 *)0x1022800c, 0x004d0000}, + {(u32 *)0x10228c18, 0x06460740}, + {(u32 *)0x10228c98, 0x06460740}, + {(u32 *)0x10228d18, 0x064607c0}, + {(u32 *)0x1022818c, 0x000ba000}, + {(u32 *)0x1022808c, 0x0002e800}, + {(u32 *)0x1022810c, 0x0002e800}, + {(u32 *)0x10228188, 0x00000800}, + {(u32 *)0x10228088, 0x00000800}, + {(u32 *)0x10228108, 0x00000800}, + {(u32 *)0x10228188, 0x00000800}, + {(u32 *)0x10228088, 0x00000000}, + {(u32 *)0x10228108, 0x00000000}, + {(u32 *)0x10228284, 0x0000001f}, + {(u32 *)0x10228188, 0x00000801}, + {(u32 *)0x10228088, 0x00000001}, + {(u32 *)0x10228108, 0x00000001}, + {(u32 *)0x102281a0, 0x00000000}, + {(u32 *)0x102280b4, 0x00000040}, + {(u32 *)0x10228134, 0x00000040}, + {(u32 *)0x102281b4, 0x00000040}, + {(u32 *)0x1022a024, 0x00100400}, + {(u32 *)0x10232024, 0x00100400}, + {(u32 *)0x10228d94, 0x8a000003}, + {(u32 *)0x10228d9c, 0x8a000003}, + {(u32 *)0x10228db8, 0x00000002}, + {(u32 *)0x10228dd0, 0x00000002}, + {(u32 *)0x10228db8, 0x02080002}, + {(u32 *)0x10228dd0, 0x02080002}, + {(u32 *)0x10228dbc, 0x0d960000}, + {(u32 *)0x10228dd4, 0x0d960000}, + + {(u32 *)0x10230d90, 0x00000000}, + {(u32 *)0x10230d98, 0x00000000}, + {(u32 *)0x10230270, 0x00090909}, + {(u32 *)0x10230308, 0x00000003}, + {(u32 *)0x10230d00, 0x00144010}, + {(u32 *)0x10232210, 0x00000000}, + {(u32 *)0x10230d34, 0xc0778609}, + {(u32 *)0x10230d38, 0x0004e101}, + {(u32 *)0x10230d18, 0x00060740}, + {(u32 *)0x102300b4, 0x00000055}, + {(u32 *)0x10230134, 0x00000055}, + {(u32 *)0x102301b4, 0x00000055}, + {(u32 *)0x102301a0, 0x00200000}, + {(u32 *)0x10230284, 0x0000000f}, + {(u32 *)0x10230c18, 0x00060740}, + {(u32 *)0x10230c98, 0x00060740}, + {(u32 *)0x10230d18, 0x00060740}, + {(u32 *)0x1023000c, 0x00000000}, + {(u32 *)0x10230000, 0x00000000}, + {(u32 *)0x10230004, 0x00000000}, + {(u32 *)0x10230188, 0x00000000}, + {(u32 *)0x10230088, 0x00000000}, + {(u32 *)0x10230108, 0x00000000}, + {(u32 *)0x10230088, 0x880aec00}, + {(u32 *)0x10230108, 0x880aec00}, + {(u32 *)0x10230188, 0x880bac00}, + {(u32 *)0x10230180, 0x00000000}, + {(u32 *)0x10230080, 0x00000000}, + {(u32 *)0x10230100, 0x00000000}, + {(u32 *)0x10230da0, 0x00040000}, + {(u32 *)0x10230da8, 0x00040000}, + {(u32 *)0x10230d94, 0x8a000000}, + {(u32 *)0x10230d9c, 0x8a000000}, + {(u32 *)0x10230180, 0x00000002}, + {(u32 *)0x10230080, 0x00000002}, + {(u32 *)0x10230100, 0x00000002}, + {(u32 *)0x10230184, 0x00200000}, + {(u32 *)0x10230084, 0x00000000}, + {(u32 *)0x10230104, 0x00000000}, + {(u32 *)0x10230c18, 0x02460740}, + {(u32 *)0x10230c98, 0x02460740}, + {(u32 *)0x10230d18, 0x02460740}, + {(u32 *)0x10230180, 0x0000000a}, + {(u32 *)0x10230080, 0x0000000a}, + {(u32 *)0x10230100, 0x0000000a}, + {(u32 *)0x10230000, 0x80000000}, + {(u32 *)0x10230004, 0x80000000}, + {(u32 *)0x1023000c, 0x00410000}, + {(u32 *)0x10230c18, 0x06460740}, + {(u32 *)0x10230c98, 0x06460740}, + {(u32 *)0x10230d18, 0x06460740}, + {(u32 *)0x1023018c, 0x0003a000}, + {(u32 *)0x1023008c, 0x0002e800}, + {(u32 *)0x1023010c, 0x0002e800}, + {(u32 *)0x10230188, 0x00000800}, + {(u32 *)0x10230088, 0x00000800}, + {(u32 *)0x10230108, 0x00000800}, + {(u32 *)0x10230188, 0x00000800}, + {(u32 *)0x10230088, 0x00000000}, + {(u32 *)0x10230108, 0x00000000}, + {(u32 *)0x10230284, 0x0000001f}, + {(u32 *)0x10230188, 0x00000801}, + {(u32 *)0x10230088, 0x00000001}, + {(u32 *)0x10230108, 0x00000001}, + {(u32 *)0x102301a0, 0x00000000}, + {(u32 *)0x102300b4, 0x00000040}, + {(u32 *)0x10230134, 0x00000040}, + {(u32 *)0x102301b4, 0x00000040}, + {(u32 *)0x1022a024, 0x00100400}, + {(u32 *)0x10232024, 0x00100400}, + {(u32 *)0x10230d94, 0x00000001}, + {(u32 *)0x10230d9c, 0x00000001}, + {(u32 *)0x10230db8, 0x00000002}, + {(u32 *)0x10230dd0, 0x00000002}, + {(u32 *)0x10230db8, 0x02080000}, + {(u32 *)0x10230dd0, 0x02080000}, + {(u32 *)0x10230dbc, 0x0d960000}, + {(u32 *)0x10230dd4, 0x0d960000}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x1022a028, 0x20080000}, + {(u32 *)0x1022a024, 0x08100400}, + {(u32 *)0x1022a004, 0x30822201}, + {(u32 *)0x1022a064, 0x200007d2}, + {(u32 *)0x102280bc, 0x10000011}, + {(u32 *)0x1022813c, 0x10000011}, + {(u32 *)0x1022ab04, 0x0f0f0f0f}, + {(u32 *)0x1022a204, 0x00014310}, + {(u32 *)0x1022ac54, 0x80200608}, + {(u32 *)0x1022a8a8, 0x14a5294a}, + {(u32 *)0x1022a8ac, 0x14a5294a}, + {(u32 *)0x1022a8b0, 0x14a5294a}, + {(u32 *)0x1022a8b4, 0x14a5294a}, + {(u32 *)0x1022a0dc, 0x0001d00a}, + {(u32 *)0x1022a210, 0x00000001}, + {(u32 *)0x1022a000, 0x04109000}, + {(u32 *)0x1022a208, 0x70000010}, + {(u32 *)0x1022a208, 0x50000010}, + {(u32 *)0x1022a03c, 0x020c0000}, + {(u32 *)0x102280bc, 0x10100011}, + {(u32 *)0x1022813c, 0x10100011}, + {(u32 *)0x102281c0, 0x00000000}, + {(u32 *)0x1022829c, 0xb901020f}, + {(u32 *)0x102282a0, 0x8100908c}, + {(u32 *)0x102302a0, 0x8100908c}, + {(u32 *)0x102285f0, 0x01000222}, + {(u32 *)0x10228670, 0x01000222}, + {(u32 *)0x102286f0, 0x00000000}, + {(u32 *)0x102281b4, 0x00000000}, + {(u32 *)0x102280b4, 0x00000000}, + {(u32 *)0x10228134, 0x00000000}, + {(u32 *)0x1022a840, 0xa10810bf}, + {(u32 *)0x1022a860, 0xc0010003}, + {(u32 *)0x10228c1c, 0x00008010}, + {(u32 *)0x10228c9c, 0x00008000}, + {(u32 *)0x1022a04c, 0x25712000}, + {(u32 *)0x1022a880, 0x00000000}, + {(u32 *)0x1022a884, 0x00070000}, + {(u32 *)0x1022a888, 0x00000000}, + {(u32 *)0x1022a88c, 0x00000000}, + {(u32 *)0x1022a890, 0x11111011}, + {(u32 *)0x1022a8a0, 0x33333333}, + {(u32 *)0x1022a8a4, 0x11114444}, + + {(u32 *)0x1022aa2c, 0x33333333}, + {(u32 *)0x1022aa30, 0x33333333}, + {(u32 *)0x1022aa34, 0x22226666}, + {(u32 *)0x1022aa38, 0x22226666}, + {(u32 *)0x1022ab2c, 0x33333333}, + {(u32 *)0x1022ab30, 0x33333333}, + {(u32 *)0x1022ab34, 0x22226666}, + {(u32 *)0x1022ab38, 0x22226666}, + {(u32 *)0x10228e1c, 0x001a1a00}, + {(u32 *)0x10228f1c, 0x00141400}, + {(u32 *)0x10228e6c, 0x001a1a00}, + {(u32 *)0x10228f6c, 0x00141400}, + {(u32 *)0x102280bc, 0x10100031}, + {(u32 *)0x102280b0, 0x010350c0}, + {(u32 *)0x1022813c, 0x10100031}, + {(u32 *)0x10228130, 0x010350c0}, + {(u32 *)0x1022a200, 0xf0100000}, + {(u32 *)0x1022a048, 0x08400000}, + {(u32 *)0x1022a85c, 0x33210000}, + {(u32 *)0x1022a878, 0xc0000000}, + {(u32 *)0x1022a024, 0x88102400}, + {(u32 *)0x1022a034, 0x00731004}, + {(u32 *)0x1022a848, 0x9007000f}, + {(u32 *)0x1022a064, 0x240007d2}, + {(u32 *)0x1022a0d8, 0x00000040}, + {(u32 *)0x1022a0d4, 0x0001c110}, + {(u32 *)0x1022a050, 0x30000700}, + {(u32 *)0x1022a054, 0x6543b321}, + {(u32 *)0x1022a004, 0x30822001}, + {(u32 *)0x1022a008, 0x81080000}, + {(u32 *)0x1022a00c, 0x00024f13}, + {(u32 *)0x1022a010, 0x00000080}, + {(u32 *)0x1022a020, 0x00000009}, + {(u32 *)0x1022a038, 0x80000106}, + {(u32 *)0x1022a040, 0x3000000c}, + {(u32 *)0x1022a04c, 0x25714001}, + {(u32 *)0x1022a858, 0x64400000}, + {(u32 *)0x1022aa04, 0x00001919}, + {(u32 *)0x1022ab04, 0x00001b1b}, + {(u32 *)0x1022a004, 0x308a2001}, + {(u32 *)0x1022a058, 0x00000a56}, + {(u32 *)0x1022a84c, 0x00ff0000}, + {(u32 *)0x1022a04c, 0x65714001}, + {(u32 *)0x1022a048, 0x48400000}, + {(u32 *)0x1022a06c, 0x00020000}, + {(u32 *)0x1022a038, 0xc0000106}, + {(u32 *)0x1022a038, 0xc0000107}, + {(u32 *)0x1022a20c, 0x00010000}, + {(u32 *)0x1022a204, 0x00014f10}, + {(u32 *)0x1022a09c, 0x12000480}, + {(u32 *)0x1022a01c, 0x57000000}, + {(u32 *)0x1022a01c, 0x17000000}, + {(u32 *)0x1022a074, 0x00000068}, + {(u32 *)0x1022a00c, 0x000a4f13}, + {(u32 *)0x1022a01c, 0x07000000}, + {(u32 *)0x1022a034, 0x00731804}, + {(u32 *)0x1022a064, 0x340007d2}, + {(u32 *)0x1022a20c, 0x00010004}, + {(u32 *)0x1022a004, 0x308a2000}, + {(u32 *)0x1022a06c, 0x00020000}, + {(u32 *)0x1022a8c0, 0xa0000000}, + {(u32 *)0x10228c1c, 0x00008090}, + {(u32 *)0x10228c9c, 0x00008080}, + {(u32 *)0x1022a858, 0x64400000}, + {(u32 *)0x1022aa2c, 0x33333322}, + {(u32 *)0x1022aa30, 0x33333322}, + {(u32 *)0x1022ab2c, 0x33333322}, + {(u32 *)0x1022ab30, 0x33333322}, + {(u32 *)0x1022a204, 0x00034f10}, + {(u32 *)0x1022a204, 0x00014f10}, + {(u32 *)0x1022a200, 0xfc100001}, + {(u32 *)0x1022a204, 0x00014f50}, + {(u32 *)0x1022a8c4, 0x02009800}, + {(u32 *)0x1022829c, 0xb9010200}, + {(u32 *)0x1022a850, 0x00000100}, + {(u32 *)0x1022a200, 0xfc120001}, + {(u32 *)0x10228c1c, 0x00008090}, + {(u32 *)0x10228c9c, 0x00008080}, + {(u32 *)0x1022a850, 0x00000110}, + {(u32 *)0x1022a850, 0x00000112}, + {(u32 *)0x1022a050, 0x30000721}, + {(u32 *)0x1022a0c8, 0x098e0080}, + {(u32 *)0x1022a01c, 0x00000000}, + {(u32 *)0x1022a034, 0x00731814}, + {(u32 *)0x1022a858, 0x64400000}, + {(u32 *)0x1022a8c0, 0x20000000}, + {(u32 *)0x1022aa0c, 0x1a1a1a1a}, + {(u32 *)0x1022ab0c, 0x14141414}, + {(u32 *)0x1022aa34, 0x44446666}, + {(u32 *)0x1022aa38, 0x44446666}, + {(u32 *)0x1022ab34, 0x44446666}, + {(u32 *)0x1022ab38, 0x44446666}, + {(u32 *)0x1022ac54, 0x8120050c}, + {(u32 *)0x10228c1c, 0x0000b090}, + {(u32 *)0x10228c9c, 0x0000b080}, + {(u32 *)0x1022a8d0, 0x00000000}, +// dramc_setting_DDR3600 + {(u32 *)0x1022a8a0, 0x33334444}, + {(u32 *)0x1022a8a4, 0x66661111}, +// update_initial_settings + {(u32 *)0x1022a860, 0xc0010003}, + {(u32 *)0x10228c1c, 0x0000b090}, + {(u32 *)0x10228c9c, 0x0000b080}, + {(u32 *)0x10228608, 0x20000000}, + {(u32 *)0x10228808, 0x20000000}, + {(u32 *)0x10228688, 0x20000000}, + {(u32 *)0x10228888, 0x20000000}, + {(u32 *)0x10228d1c, 0x00000000}, + {(u32 *)0x102281a4, 0x0000048c}, + {(u32 *)0x102281c0, 0x00000020}, + {(u32 *)0x102281b0, 0x00024000}, + {(u32 *)0x102280a4, 0x000004ee}, + {(u32 *)0x10228124, 0x000004ee}, + {(u32 *)0x102281a4, 0x000004ac}, + {(u32 *)0x102280a4, 0x000004ec}, + {(u32 *)0x10228124, 0x000004ec}, + {(u32 *)0x102280ac, 0x82110e00}, + {(u32 *)0x1022812c, 0x82110e00}, + {(u32 *)0x102281ac, 0x80000808}, + {(u32 *)0x102281b0, 0x00034000}, + {(u32 *)0x10228268, 0x00000020}, + {(u32 *)0x102280b0, 0x010352c0}, + {(u32 *)0x10228130, 0x010352c0}, + {(u32 *)0x102281b0, 0x00034200}, + {(u32 *)0x102280b0, 0x010352c1}, + {(u32 *)0x10228130, 0x010352c1}, + {(u32 *)0x102281b0, 0x00034201}, + {(u32 *)0x102281b0, 0x00034241}, + {(u32 *)0x102280b0, 0x010352c9}, + {(u32 *)0x10228130, 0x010352c9}, + {(u32 *)0x102281b0, 0x00034249}, + {(u32 *)0x102280b0, 0x010352e9}, + {(u32 *)0x10228130, 0x010352e9}, + {(u32 *)0x102281b0, 0x00034269}, + {(u32 *)0x10228c14, 0x00300016}, + {(u32 *)0x102280ac, 0x82111600}, + {(u32 *)0x10228c94, 0x00300016}, + {(u32 *)0x1022812c, 0x82111600}, + {(u32 *)0x102280b8, 0x00000007}, + {(u32 *)0x10228138, 0x00000007}, + {(u32 *)0x102281bc, 0x00010007}, + {(u32 *)0x1022a204, 0x00014f70}, + {(u32 *)0x1022a200, 0xfc120001}, + {(u32 *)0x102280b0, 0x010392e9}, + {(u32 *)0x102280bc, 0x10100031}, + {(u32 *)0x102280bc, 0x10100020}, + {(u32 *)0x102280bc, 0x10100031}, + {(u32 *)0x10228130, 0x010392e9}, + {(u32 *)0x1022813c, 0x10100031}, + {(u32 *)0x1022813c, 0x10100020}, + {(u32 *)0x1022813c, 0x10100031}, + {(u32 *)0x102300b8, 0x00000007}, + {(u32 *)0x10230138, 0x00000007}, + {(u32 *)0x102301bc, 0x00010007}, + {(u32 *)0x10232204, 0x00014f70}, + {(u32 *)0x10232200, 0xfc120001}, + {(u32 *)0x102300b0, 0x010392e9}, + {(u32 *)0x102300bc, 0x10100031}, + {(u32 *)0x102300bc, 0x10100020}, + {(u32 *)0x102300bc, 0x10100031}, + {(u32 *)0x10230130, 0x010392e9}, + {(u32 *)0x1023013c, 0x10100031}, + {(u32 *)0x1023013c, 0x10100020}, + {(u32 *)0x1023013c, 0x10100031}, + {(u32 *)0x102281b8, 0x00080a0a}, + {(u32 *)0x102281b8, 0x00080a0a}, + {(u32 *)0x1022a8cc, 0x0000f132}, + {(u32 *)0x1022a8c4, 0x02a19800}, + {(u32 *)0x10228c14, 0x00300016}, + {(u32 *)0x10228c94, 0x00300016}, + {(u32 *)0x10228d14, 0x00000000}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x10228c18, 0x06460740}, + {(u32 *)0x10228c98, 0x06460740}, + {(u32 *)0x10228d18, 0x064607c0}, + {(u32 *)0x10230c18, 0x06460740}, + {(u32 *)0x10230c98, 0x06460740}, + {(u32 *)0x10230d18, 0x06460740}, + {(u32 *)0x100010b4, 0x0000001f}, + {(u32 *)0x1022a864, 0x81080004}, + {(u32 *)0x1022a048, 0x4840f000}, + {(u32 *)0x1022a218, 0x00020000}, + {(u32 *)0x1022a8cc, 0x0000f132}, + {(u32 *)0x10228c20, 0xffc07fff}, + {(u32 *)0x10228ca0, 0xffc07fff}, + {(u32 *)0x10228d20, 0xffc07fff}, + {(u32 *)0x102282a8, 0x15351135}, + {(u32 *)0x10228c1c, 0x00008090}, + {(u32 *)0x10228c9c, 0x00008080}, + {(u32 *)0x1022a03c, 0x020cffff}, + {(u32 *)0x1022ac54, 0x8120050c}, + {(u32 *)0x1022a0bc, 0x00080000}, + {(u32 *)0x1022a0d0, 0x01000000}, + {(u32 *)0x1022a208, 0x50000010}, + {(u32 *)0x1022a20c, 0x00010704}, + {(u32 *)0x1022a860, 0xc001000f}, + {(u32 *)0x10228c34, 0xc0778609}, + {(u32 *)0x10228cb4, 0xc0778609}, + {(u32 *)0x10228184, 0x00200000}, + {(u32 *)0x1022a00c, 0x040acf13}, + {(u32 *)0x1022a048, 0x4840f000}, + {(u32 *)0x1022a0d8, 0x0000001a}, + {(u32 *)0x102280b0, 0x010392e9}, + {(u32 *)0x10228130, 0x010392e9}, + {(u32 *)0x102281b0, 0x000352e9}, + {(u32 *)0x1022a208, 0x50010010}, + {(u32 *)0x10228c1c, 0x13008090}, + {(u32 *)0x10228c9c, 0x13008080}, + {(u32 *)0x1022a874, 0x00000000}, + {(u32 *)0x1022a8c4, 0x02a19800}, + {(u32 *)0x1022aa08, 0x00000000}, + {(u32 *)0x1022ab08, 0x00000000}, + {(u32 *)0x1022a850, 0x00000112}, + {(u32 *)0x102280bc, 0x10100431}, + {(u32 *)0x1022813c, 0x10100431}, + {(u32 *)0x102281c0, 0x00000020}, + {(u32 *)0x10228c20, 0xffc07fff}, + {(u32 *)0x10228ca0, 0xffc07fff}, + {(u32 *)0x10228c38, 0x00032401}, + {(u32 *)0x10228cb8, 0x00032401}, + {(u32 *)0x1022a860, 0xc001000f}, + {(u32 *)0x10228c1c, 0x13008090}, + {(u32 *)0x10228c9c, 0x13008080}, + {(u32 *)0x1022a028, 0x20080000}, + {(u32 *)0x1022a04c, 0x75714001}, + {(u32 *)0x1022a058, 0x00080a56}, + {(u32 *)0x1022a0d0, 0x0d000000}, + {(u32 *)0x1022a0dc, 0x0001d10a}, + {(u32 *)0x1022a0e0, 0x0b80000d}, + {(u32 *)0x102282a8, 0x1d351135}, + {(u32 *)0x10228084, 0x00300000}, + {(u32 *)0x10228104, 0x00300000}, + {(u32 *)0x10228184, 0x00300000}, + {(u32 *)0x1022829c, 0xb1010200}, + {(u32 *)0x102285e8, 0x00000101}, + {(u32 *)0x1022a040, 0x3000008c}, + {(u32 *)0x1022a050, 0x300007a1}, + {(u32 *)0x1022a0d4, 0x0c01c1d0}, + {(u32 *)0x1022a0dc, 0x8001dd0a}, + {(u32 *)0x1022a208, 0x50010000}, + {(u32 *)0x1022a218, 0x00020000}, + {(u32 *)0x1022a024, 0x88502400}, + {(u32 *)0x102281d0, 0xa94011c0}, + {(u32 *)0x1022a024, 0x88d02400}, + {(u32 *)0x1022a874, 0x00000000}, + {(u32 *)0x1022a0a0, 0x0080110d}, + {(u32 *)0x1022a84c, 0x00ff0005}, + {(u32 *)0x1022a04c, 0x75774001}, + {(u32 *)0x1022a0dc, 0x8301dd0a}, + {(u32 *)0x1022a04c, 0x75774001}, + {(u32 *)0x1022a004, 0x348a2000}, + {(u32 *)0x1022a0d0, 0x0d426810}, + {(u32 *)0x1022a0a0, 0x4080110d}, + {(u32 *)0x1022a004, 0x348a2000}, + {(u32 *)0x100010b4, 0x00000000}, + {(u32 *)0x1022a0d4, 0x0c03c1d0}, + {(u32 *)0x1022a0dc, 0x8301dd0a}, + {(u32 *)0x102320d4, 0x0c01c1f0}, + {(u32 *)0x102320dc, 0x8301cd0a}, +}; + +static void dramc_power_on_sequence(void) +{ + u8 chn; + + /* reset dram = low */ + for (chn = 0; chn < CHANNEL_MAX; chn++) + clrbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 13)); + + /* CKE low */ + dramc_cke_fix_onoff(CHANNEL_A, false, true); + dramc_cke_fix_onoff(CHANNEL_B, false, true); + + /* delay tINIT1=200us(min) & tINIT2=10ns(min)*/ + udelay(200); + + for (chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 13)); + + /* Disable HW MIOCK control to make CLK always on */ + for (chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].ao.dramc_pd_ctrl, (0x1 << 26)); + + udelay(2000); + + /* CKE high */ + dramc_cke_fix_onoff(CHANNEL_A, true, false); + dramc_cke_fix_onoff(CHANNEL_B, true, false); + udelay(2); +} + +static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay) +{ + u8 dly, dlyb, revb0, revb1; + + dly = (clkDelay < 0) ? -clkDelay : 0; + dlyb = (clkDelay < 0) ? 0 : clkDelay; + revb0 = dly ? 1 : 0; + revb1 = dlyb ? 1 : 0; + + for (u8 r = 0; r < RANK_MAX; r++) { + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], + (0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28)); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], + (0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28)); } + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3], + (0x3 << 8), (revb0 << 8) | (revb1 << 9)); +} + +static void dramc_duty_set_dqs_delay(u8 chn, s8* s_dqsDelay) +{ + u8 dly, dlyb, revb0, revb1; + s8 dqsDelay ; + + for (u8 r = 0; r < RANK_MAX; r++) + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dqsDelay = s_dqsDelay[dqs] ; + + dly = (dqsDelay < 0) ? -dqsDelay : 0; + dlyb = (dqsDelay < 0) ? 0 : dqsDelay; + revb0 = dly ? 1 : 0; + revb1 = dlyb ? 1 : 0; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], + (0xf << 24) | (0xf << 28) | + (0xf << 16) | (0xf << 20), + (dly << 24) | (dly << 28) | + (dlyb << 16) | (dlyb << 20)); + } + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1], + 0x3 << 8, (revb0 << 8) | (revb1 << 9)); +} + +static void dramc_duty_calibration(const struct sdram_params *params, u32 freq_group) +{ + s8 clkDelay[CHANNEL_MAX]; + s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER]; + + if (freq_group == LP4X_DDR3200) { + clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 1; + dqsDelay[CHANNEL_A][1] = -2; + dqsDelay[CHANNEL_B][0] = 1; + dqsDelay[CHANNEL_B][1] = -2; + } else if (freq_group == LP4X_DDR3600) { + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + } else { + clkDelay[CHANNEL_A] = 2; + clkDelay[CHANNEL_B] = 1; + dqsDelay[CHANNEL_A][0] = 0; + dqsDelay[CHANNEL_A][1] = 0; + dqsDelay[CHANNEL_B][0] = -1; + dqsDelay[CHANNEL_B][1] = 0; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay(chn, clkDelay[chn]); + dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + } +} + +#define TIME_OUT_CNT 100 //100us +static u8 dramc_zq_calibration(u8 chn, u8 rank) +{ + u32 resp, u4TimeCnt; + struct reg_value regs_bak[] = { + {&ch[chn].ao.mrs, 0x0}, + {&ch[chn].ao.dramc_pd_ctrl, 0x0}, + {&ch[chn].ao.ckectrl, 0x0}, + }; + + dramc_dbg("[%s] rank:%d\n", __func__, rank); + u4TimeCnt = TIME_OUT_CNT; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + dramc_cke_fix_onoff(chn, true, false); + + clrsetbits_le32(&ch[chn].ao.mrs, + MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); + setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + do { + resp = (read32(&ch[chn].nao.spcmdresp) & + (0x1 << SPCMDRESP_ZQC_RESPONSE_SHIFT)) >> + SPCMDRESP_ZQC_RESPONSE_SHIFT; + u4TimeCnt--; + udelay(1); + } while ((resp == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0) { + dramc_dbg("ZQCAL Start fail (time out)\n"); + return 1; + } + + clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); + + udelay(1); + u4TimeCnt = TIME_OUT_CNT; + + setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + do { + resp = (read32(&ch[chn].nao.spcmdresp) & + (0x1 << SPCMDRESP_ZQLAT_RESPONSE_SHIFT)) >> + SPCMDRESP_ZQLAT_RESPONSE_SHIFT; + u4TimeCnt--; + udelay(1); + } while ((resp == 0) && (u4TimeCnt > 0)); + + if (u4TimeCnt == 0) { + dramc_dbg("ZQCAL Latch fail (time out)\n"); + return 1; + } + + clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); + + udelay(1); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + return 0; +} + +#define MR13_RRO 1 +u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { + {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} }, +}; + +u8 MR14Value_06VDDQ[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { + {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} }, +}; + +u8 MR01Value[FSP_MAX] = {0x26, 0x56}; +u8 MR13Value = (MR13_RRO<<4) | (1<<3); + +u8 MR02Value[FSP_MAX] = {0x12, 0x12}; +u8 MR03Value = 0x30; +u8 MR11Value[FSP_MAX] = {0x0, 0x23}; +u8 MR22Value[FSP_MAX] = {0x38, 0x38}; + +static void dramc_mode_reg_init(u32 freq_group) +{ + MR01Value[FSP_0] &= 0x8F; + MR01Value[FSP_1] &= 0x8F; + + if (freq_group == LP4X_DDR1600) { + MR02Value[0] = 0x12; + MR02Value[1] = 0x00; + + MR01Value[FSP_0] |= (0x5 << 4); + MR01Value[FSP_1] |= (0x5 << 4); + } else if (freq_group == LP4X_DDR3200) { + MR02Value[0] = 0x00; + MR02Value[1] = 0x2d; + + MR01Value[FSP_0] |= (0x5 << 4); + MR01Value[FSP_1] |= (0x5 << 4); + } else if (freq_group == LP4X_DDR3600) { + MR02Value[0] = 0x00; + MR02Value[1] = 0x36; + + MR01Value[FSP_0] |= (0x6 << 4); + MR01Value[FSP_1] |= (0x6 << 4); + } + + u8 operate_fsp = (freq_group == LP4X_DDR1600) ? FSP_0 : FSP_1; + dramc_dbg("%s operate_fsp:%d, freq:%d\n", __func__, operate_fsp, freq_group); + + u8 chn, rank; + u32 broadcast_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_power_on_sequence(); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (rank = 0; rank < 2; rank++) { + dramc_dbg("%s CH%u RK%u, freq:%d\n", __func__, chn, rank, freqTbl[freq_group]); + clrsetbits_le32(&ch[chn].ao.mrs, + (0x3 << 24), (rank << 24)); + + /* ZQ calibration should be done before CBT calibration + * by switching to low frequency */ + dramc_zq_calibration(chn, rank); + + for (uint32_t fsp = FSP_0; fsp < FSP_MAX; fsp++) { + dramc_dbg("chn:%d,rank:%d,fsp%d\n", + chn, rank, fsp); + + if (fsp == FSP_0) + MR13Value = (MR13_RRO<<4) | (1<<3); + else + MR13Value |= 0x40; //OP[6]=1 + dramc_mode_reg_write(chn, + 0xd, MR13Value); + + /* MR12 use previous value + * MR12 VREF-CA */ + dramc_mode_reg_write(chn, + 0xc, MR12Value[chn][rank][fsp]); + dramc_mode_reg_write(chn, + 0x1, MR01Value[fsp]); + dramc_mode_reg_write(chn, + 0x2, MR02Value[fsp]); + dramc_mode_reg_write(chn, + 0xb, MR11Value[fsp]); /* ODT */ + + /* SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA */ + dramc_mode_reg_write(chn, + 0x16, MR22Value[fsp]); + + /* MR14 use previous value + * MR14 VREF-DQ */ + dramc_mode_reg_write(chn, 0xe, + MR14Value_06VDDQ[chn][rank][fsp]); + + /* MR3 set write-DBI and read-DBI */ + dramc_mode_reg_write(chn, 0x3, MR03Value); + } + + /* freq < 1333 is assumed to be odt_off -> uses FSP_0 */ + if (operate_fsp == FSP_0) + { + MR13Value &= 0x3f; //[7]FSP_OP=0, [6]FSP_WR=0 + } + else + { + MR13Value |= 0xc0; //[7]FSP_OP=1, [6]FSP_WR=1 + } + + dramc_mode_reg_write(chn, 0xd, MR13Value); + } + dramc_dbg("%s with MR13Value:%d,operate_fsp:%d,MR02Value[fsp]%d\n", __func__, + MR13Value, operate_fsp, MR02Value[operate_fsp]); + + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13, + (0x1fff << 0) | (0xff << 16), + (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg, + (0x1fff << 0) | (0xff << 16), + (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2, + (0x1fff << 0) | (0xff << 16), + (2 << 0) | (MR02Value[operate_fsp] << 16)); + } + + clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); + + dramc_set_broadcast(broadcast_bak); +} +typedef struct +{ + u8 dqsinctl; + u8 datlat; + u8 trcd; + u8 trrd; + u8 twr; + u8 twtr; + u8 trc; + u8 tras; + u8 trp; + u8 trpab; + u8 tfaw; + u8 trtw_ODT_on; + u8 trtp; + u8 txp; + u8 refcnt; + u8 trfc; + u8 trfcpb; + u8 tzqcs; + u8 refcnt_fr_clk; + u8 txrefcnt; + u8 tmrr2w_ODT_on; + u8 twtpd; + u8 trtpd; + u8 xrtw2w; + u8 xrtw2r; + u8 xrtr2w; + u8 xrtr2r; + u8 twtr_05T; + u8 trtw_ODT_on_05T; + u8 twtpd_05T; + u8 trtpd_05T; + u8 tfaw_05T; + u8 trrd_05T; + u8 twr_05T; + u8 tras_05T; + u8 trpab_05T; + u8 trp_05T; + u8 trcd_05T; + u8 trtp_05T; + u8 txp_05T; + u8 trfc_05T; + u8 trfcpb_05T; + u8 trc_05T; + u8 r_dmcatrain_intv; + u8 r_dmmrw_intv; + u8 r_dmfspchg_prdcnt; + u8 ckeprd; + u8 ckelckcnt; + u8 zqlat2; +}ACTime_T; + +const ACTime_T AC_Timing_Tbl[LP4X_DDRFREQ_MAX] = +{ +// LP4-1600, 800MHz, RDBI_OFF, normal mode +{ + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 0, .trpab_05T = 1, + .trc = 4, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .trrd = 0, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .trtw_ODT_on = 4, .trtw_ODT_on_05T = 0, + .refcnt = 48, + .refcnt_fr_clk = 101, + .txrefcnt = 62, + .tzqcs = 16, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 3, + .xrtr2r = 8, + .r_dmcatrain_intv = 8, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 50, + .trtpd = 6, .trtpd_05T = 0, + .twtpd = 6, .twtpd_05T = 0, + .tmrr2w_ODT_on = 5, + .ckeprd = 1, + .ckelckcnt = 0, + .zqlat2 = 6, + .dqsinctl = 1, .datlat = 10 +}, +// LP4-3200, 1600MHz, RDBI_OFF, normal mode +{ + .tras = 8, .tras_05T = 1, + .trp = 5, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 7, .tfaw_05T = 0, + .trtw_ODT_on = 7, .trtw_ODT_on_05T = 0, + .refcnt = 97, + .refcnt_fr_clk = 101, + .txrefcnt = 119, + .tzqcs = 34, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 6, + .xrtr2r = 9, + .r_dmcatrain_intv = 11, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 100, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 12, .twtpd_05T = 1, + .tmrr2w_ODT_on = 10, + .ckeprd = 2, + .ckelckcnt = 0, + .zqlat2 = 12, + .dqsinctl = 4, .datlat = 15 +}, + // LP4-3600, 1800MHz, RDBI_OFF, normal mode +{ + .tras = 11, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 1, .trpab_05T = 1, + .trc = 20, .trc_05T = 1, + .trfc = 118, .trfc_05T = 1, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 1, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 7, .trcd_05T = 1, + .twr = 14, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 10, .tfaw_05T = 0, + .trtw_ODT_on = 8, .trtw_ODT_on_05T = 0, + .refcnt = 113, + .refcnt_fr_clk = 101, + .txrefcnt = 138, + .tzqcs = 40, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 7, + .xrtr2r = 9, + .r_dmcatrain_intv = 13, + .r_dmmrw_intv = 0xf, //Berson: LP3/4 both use this field -> Formula may change, set to 0xF for now + .r_dmfspchg_prdcnt = 117, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_ODT_on = 11, + .ckeprd = 3, + .ckelckcnt = 0, + .zqlat2 = 14, + .dqsinctl = 6, .datlat = 18 + }, +}; + +typedef struct +{ + u8 u1TRFC : 8; + u8 u1TRFRC_05T : 1; + u16 u2TXREFCNT : 10; +} optimizeACTimexxx; + +static void ddr_update_ac_timing(u32 freq_group) +{ + u32 temp; + u8 u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0; + + u8 dqsinctl, datlat, new_datlat, trcd, trrd, twr, twtr, trc, tras; + u8 trp, trpab, tfaw, trtw_ODT_on, trtp, txp, refcnt; + u8 trfc, trfcpb, tzqcs, refcnt_fr_clk, txrefcnt, tmrr2w_ODT_on; + u8 twtpd, trtpd, xrtw2w, xrtw2r, xrtr2w, xrtr2r, twtr_05T; + u8 trtw_ODT_on_05T, twtpd_05T, trtpd_05T, tfaw_05T, trrd_05T; + u8 twr_05T, tras_05T, trpab_05T, trp_05T, trcd_05T, trtp_05T; + u8 txp_05T, trfc_05T, trfcpb_05T, trc_05T, r_dmcatrain_intv; + u8 r_dmmrw_intv, r_dmfspchg_prdcnt, ckeprd, ckelckcnt, zqlat2; + + dqsinctl = AC_Timing_Tbl[freq_group].dqsinctl; + datlat = AC_Timing_Tbl[freq_group].datlat; + new_datlat = AC_Timing_Tbl[freq_group].datlat - 2; + trcd = AC_Timing_Tbl[freq_group].trcd; + trrd = AC_Timing_Tbl[freq_group].trrd; + twr = AC_Timing_Tbl[freq_group].twr; + twtr = AC_Timing_Tbl[freq_group].twtr; + trc = AC_Timing_Tbl[freq_group].trc; + tras = AC_Timing_Tbl[freq_group].tras; + trp = AC_Timing_Tbl[freq_group].trp; + trpab = AC_Timing_Tbl[freq_group].trpab; + tfaw = AC_Timing_Tbl[freq_group].tfaw; + trtw_ODT_on = AC_Timing_Tbl[freq_group].trtw_ODT_on; + trtp = AC_Timing_Tbl[freq_group].trtp; + txp = AC_Timing_Tbl[freq_group].txp; + refcnt = AC_Timing_Tbl[freq_group].refcnt; + trfc = AC_Timing_Tbl[freq_group].trfc; + trfcpb = AC_Timing_Tbl[freq_group].trfcpb; + tzqcs = AC_Timing_Tbl[freq_group].tzqcs; + refcnt_fr_clk = AC_Timing_Tbl[freq_group].refcnt_fr_clk; + txrefcnt = AC_Timing_Tbl[freq_group].txrefcnt; + tmrr2w_ODT_on = AC_Timing_Tbl[freq_group].tmrr2w_ODT_on; + twtpd = AC_Timing_Tbl[freq_group].twtpd; + trtpd = AC_Timing_Tbl[freq_group].trtpd; + xrtw2w = AC_Timing_Tbl[freq_group].xrtw2w; + xrtw2r = AC_Timing_Tbl[freq_group].xrtw2r; + xrtr2w = AC_Timing_Tbl[freq_group].xrtr2w; + xrtr2r = AC_Timing_Tbl[freq_group].xrtr2r; + twtr_05T = AC_Timing_Tbl[freq_group].twtr_05T; + trtw_ODT_on_05T = AC_Timing_Tbl[freq_group].trtw_ODT_on_05T; + twtpd_05T = AC_Timing_Tbl[freq_group].twtpd_05T; + trtpd_05T = AC_Timing_Tbl[freq_group].trtpd_05T; + tfaw_05T = AC_Timing_Tbl[freq_group].tfaw_05T; + trrd_05T = AC_Timing_Tbl[freq_group].trrd_05T; + twr_05T = AC_Timing_Tbl[freq_group].twr_05T; + tras_05T = AC_Timing_Tbl[freq_group].tras_05T; + trpab_05T = AC_Timing_Tbl[freq_group].trpab_05T; + trp_05T = AC_Timing_Tbl[freq_group].trp_05T; + trcd_05T = AC_Timing_Tbl[freq_group].trcd_05T; + trtp_05T = AC_Timing_Tbl[freq_group].trtp_05T; + txp_05T = AC_Timing_Tbl[freq_group].txp_05T; + trfc_05T = AC_Timing_Tbl[freq_group].trfc_05T; + trfcpb_05T = AC_Timing_Tbl[freq_group].trfcpb_05T; + trc_05T = AC_Timing_Tbl[freq_group].trc_05T; + r_dmcatrain_intv = AC_Timing_Tbl[freq_group].r_dmcatrain_intv; + r_dmmrw_intv = AC_Timing_Tbl[freq_group].r_dmmrw_intv; + r_dmfspchg_prdcnt = AC_Timing_Tbl[freq_group].r_dmfspchg_prdcnt; + ckeprd = AC_Timing_Tbl[freq_group].ckeprd; + ckelckcnt = AC_Timing_Tbl[freq_group].ckelckcnt; + zqlat2 = AC_Timing_Tbl[freq_group].zqlat2; + + if (freq_group == LP4X_DDR1600) { + u1ROOT = 0; u1TXRANKINCTL=0; u1TXDLY=1; + } else { + if (freq_group == LP4X_DDR3600) + u1ROOT = 1; + else + u1ROOT = 0; + u1TXRANKINCTL=1; u1TXDLY=2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.shu[0].actim[0], + (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0), + (trcd << 24) | (trrd << 16) | (twr << 8) | (twtr << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[1], + (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0), + (trc << 24) | (tras << 16) | (trp << 8) | (trpab << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[2], + (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0), + (tfaw << 24) | (trtw_ODT_on << 16) | (trtp << 8) | (txp << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + (0xff << 16) | (0xff << 24) | (0xff << 0), + (trfc << 16) | (refcnt << 24) | (trfcpb << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + (0xff << 24) | (0xff << 16) | (0x3ff << 0), + (tzqcs << 24) | (refcnt_fr_clk << 16) | (txrefcnt << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[5], + (0xf << 24) | (0x1f << 8) | (0x1f << 0), + (tmrr2w_ODT_on << 24) | (twtpd << 8) | (trtpd << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, + (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0), + (xrtw2w << 24) | (xrtw2r << 16) | (xrtr2w << 8) | (xrtr2r << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15)| + (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) | + (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) | + (0x1 << 4) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0), + (twtr_05T << 25) | (trtw_ODT_on_05T << 24) | (twtpd_05T << 16) | (trtpd_05T << 15) | + (tfaw_05T << 13) | (trrd_05T << 12) | (twr_05T << 10) | (tras_05T << 9) | + (trpab_05T << 8) | (trp_05T << 7) | (trcd_05T << 6) | (trtp_05T << 5) | + (txp_05T << 4) | (trfc_05T << 2) | (trfcpb_05T << 1) | (trc_05T << 0)); + clrsetbits_le32(&ch[chn].ao.catraining1, + (0xff << 24) | (0xf << 20), (r_dmcatrain_intv << 24) | (0x0 << 20)); + + /* DQSINCTL related */ + clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, + (0xf << 0), (dqsinctl << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, + (0xf << 0), (dqsinctl << 0)); + clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl, + (0xf << 4), (dqsinctl << 4)); + + /* DATLAT related, tREFBW */ + clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], + (0x1f << 0) | (0x1f << 8) | + (0x1f << 26) | (0x3ff << 16), + (datlat << 0) | (new_datlat << 8) | (new_datlat << 26) | (0x0 << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].conf[2], + (0xff << 8), (r_dmfspchg_prdcnt << 8)); + clrsetbits_le32(&ch[chn].ao.shu[0].scintv, + (0x1f << 13) | (0x1f << 6), (r_dmmrw_intv << 13) | (zqlat2 << 6)); + + /* CKEPRD - CKE pulse width */ + clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl, + (0x7 << 20), (ckeprd << 20)); + + /* CKELCKCNT: Valid clock requirement after CKE input low */ + clrsetbits_le32(&ch[chn].ao.ckectrl, (0x7 << 24), (ckelckcnt << 24)); + + temp = (read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20; + clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + (0xf << 0), (temp << 0)); + + clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + (0xf << 16) | (0xf << 12) | (0xf << 8), + (u1ROOT << 16) | (u1TXRANKINCTL << 12) | (u1TXDLY << 8)); + } + + u8 dram_cbt_mode = 0; + + setbits_le32(&ch[0].ao.arbctl, (0x3 << 10)); + clrsetbits_le32(&ch[0].ao.rstmask, (0x3 << 13), dram_cbt_mode); + clrsetbits_le32(&ch[0].ao.arbctl, (0x1 << 13), dram_cbt_mode); +} + +void dramc_init(const struct sdram_params *params, u32 freq_group) +{ + dramc_dbg("%s start\n", __func__); + if (freq_group == LP4X_DDR3200) { + for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence); i++) + write32(dramc_init_sequence[i].addr, + dramc_init_sequence[i].value); + for (int i = 0; i < ARRAY_SIZE(dramc_mode_reg_init_sequence); i++) { + write32(dramc_mode_reg_init_sequence[i].addr, + dramc_mode_reg_init_sequence[i].value); + udelay(2); + } + } else if (freq_group == LP4X_DDR3600) { + for (int i = 0; i < ARRAY_SIZE(dramc_init_sequence_3600); i++) + write32(dramc_init_sequence_3600[i].addr, + dramc_init_sequence_3600[i].value); + + dramc_duty_calibration(params, freq_group); + dramc_mode_reg_init(freq_group); + ddr_update_ac_timing(freq_group); + } + dramc_dbg("%s end\n", __func__); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 05f793e..0dc11dc 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -41,7 +41,10 @@ GATING_START = 26, GATING_END = GATING_START + 24, }; +#define WRITE_LEVELING_MOVD_DQS 1//UI
+#define TEST2_1_CAL 0x55000000 +#define TEST2_2_CAL 0xaa000400 enum CAL_TYPE { RX_WIN_RD_DQC = 0, RX_WIN_TEST_ENG, @@ -102,13 +105,13 @@ } }
-static void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off) +void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off) { clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), ((fix_on ? 1 : 0) << 6) | ((fix_off ? 1 : 0) << 7)); }
-static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) +void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) { u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl);
@@ -124,7 +127,8 @@ ;
clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); - setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); + write32(&ch[chn].ao.ckectrl, ckectrl_bak); + dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); }
static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, @@ -138,23 +142,138 @@ clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); }
+static void dramc_rank_swap(u8 chn, u8 rank) +{ + u8 multi_rank = 1; + + dramc_dbg("[RankSwap] (Multi %d), Rank %d\n", multi_rank, rank); + + clrsetbits_le32(&ch[chn].ao.rkcfg, + 0x7 << 4 | 0x1 << 7 | 0x3 <<0, + (multi_rank << 4) | (rank << 7) | (rank << 0)); + + /* TXRANK should be set before TXRANKFIX */ + clrsetbits_le32(&ch[chn].ao.rkcfg, 1 << 3, rank << 3); +} + +static void move_dramc_delay(uint32_t *reg_0, uint32_t *reg_1, + u8 shift, s8 shift_coarse_tune) +{ + s32 tmp_0p5t, tmp_2t, sum; + + tmp_0p5t = (((read32(reg_0) >> shift) & DQ_DIV_MASK) & (~(1<<DQ_DIV_SHIFT))); + tmp_2t = (read32(reg_1) >> shift) & DQ_DIV_MASK ; + + sum = (tmp_2t << DQ_DIV_SHIFT) + tmp_0p5t + shift_coarse_tune; + + if (sum < 0) { + tmp_0p5t = 0; + tmp_2t = 0; + } else { + tmp_2t = sum >> DQ_DIV_SHIFT; + tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT); + } + + clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); + clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); +} + +static void move_dramc_tx_dqs(u8 chn, u8 byte_idx, s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, + byte_idx * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dqs_oen(u8 chn, u8 byte_idx, + s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, + (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune); +} + +static void move_dramc_tx_dq(u8 chn, u8 rank, u8 byte_idx, s8 shift_coarse_tune) +{ + //DQM0 + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], + byte_idx * 4, shift_coarse_tune); + + //DQ0 + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], + byte_idx * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dq_oen(u8 chn, u8 rank, + u8 byte_idx, s8 shift_coarse_tune) +{ + //DQM_OEN_0 + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], + (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune); + //DQ_OEN_0 + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], + (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune); +} + +static void write_leveling_move_dqs_instead_of_clk(u8 chn) +{ + for (u8 byte_idx = 0; byte_idx < DQS_NUMBER; byte_idx++) { + move_dramc_tx_dqs(chn, byte_idx, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dqs_oen(chn, byte_idx, -WRITE_LEVELING_MOVD_DQS); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + move_dramc_tx_dq(chn, rk, byte_idx, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dq_oen(chn, rk, byte_idx, -WRITE_LEVELING_MOVD_DQS); + } + } +} + static void dramc_write_leveling(u8 chn, u8 rank, const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) { - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); + struct reg_value regs_bak[] = { + {&ch[chn].ao.refctrl0, 0x0}, + {&ch[chn].ao.spcmdctrl, 0x0}, + {&ch[chn].ao.dramc_pd_ctrl, 0x0}, + {&ch[chn].ao.write_lev, 0x0}, + {&ch[chn].ao.ckectrl, 0x0}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + dramc_rank_swap(chn, rank);
- for (size_t i = 0; i < DQS_NUMBER; i++) { - s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; + dramc_auto_refresh_switch(chn, false); + if (rank == RANK_0) + write_leveling_move_dqs_instead_of_clk(chn); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + + for (u8 i = 0; i < DQS_NUMBER; i++) { + u32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; + dramc_dbg("%s ch:%d, rank:%d,DQ:%d, wrlevel: %d\n", + __func__, chn, rank, i, wr_level[chn][rank][i]); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], + FINE_TUNE_PBYTE_MASK, + wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT); assert(wrlevel_dq_delay < 0x40); + if (wrlevel_dq_delay >= 0x40) { + wrlevel_dq_delay -= 0x40; + move_dramc_tx_dq(chn, rank, i, 2); + move_dramc_tx_dq_oen(chn, rank, i, 2); + }
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], - FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | - FINE_TUNE_DQ_MASK, - (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | + FINE_TUNE_DQM_MASK | FINE_TUNE_DQ_MASK, (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); } + dramc_rank_swap(chn, RANK_0); }
static void dramc_cmd_bus_training(u8 chn, u8 rank, @@ -344,10 +463,12 @@ } }
+extern u8 MR13Value; static void dramc_set_mr13_vrcg_to_Normal(u8 chn) { + MR13Value &= ~(0x1<<3); for (u8 rank = 0; rank < RANK_MAX; rank++) - dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); @@ -405,12 +526,33 @@ rank << TEST2_4_TESTAGENTRK_SHIFT); }
-static void dramc_engine2_init(u8 chn, u8 rank, u32 size, bool test_pat) +static void dramc_engine2_setpat(u8 chn, bool test_pat) { - const u32 pat0 = 0x55; - const u32 pat1 = 0xaa; - const u32 addr = 0; + clrbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | + (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | + (0x1 << TEST2_4_TESTAUDBITINV_SHIFT));
+ if (!test_pat) { + setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | + (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT), + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); + } else { + clrsetbits_le32(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, + (0x11 << 8) | (0xd << 0) | (0x1 << 14)); + } + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, + (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); +} + +static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat) +{ dramc_set_rank_engine2(chn, rank);
clrbits_le32(&ch[chn].ao.dummy_rd, @@ -420,55 +562,53 @@ (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); - clrbits_le32(&ch[chn].nao.testchip_dma1, - 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT); + clrbits_le32(&ch[chn].nao.testchip_dma1, 0x1 << 12); clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); clrsetbits_le32(&ch[chn].ao.test2_0, TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, - (pat0 << TEST2_0_PAT0_SHIFT) | - (pat1 << TEST2_0_PAT1_SHIFT)); - write32(&ch[chn].ao.test2_1, (addr << 4) & 0x00ffffff); - write32(&ch[chn].ao.test2_2, (size << 4) & 0x00ffffff); + ((t2_1 >> 24) << TEST2_0_PAT0_SHIFT) | + ((t2_2 >> 24) << TEST2_0_PAT1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.test2_1, 0xfffffff0, (t2_1 & 0x00ffffff) << 4); + clrsetbits_le32(&ch[chn].ao.test2_2, 0xfffffff0, (t2_2 & 0x00ffffff) << 4);
- clrsetbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT), - ((!test_pat ? 1 : 0) << TEST2_4_TESTXTALKPAT_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDMODE_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT)); - setbits_le32(&ch[chn].ao.perfctl0, - 0x1 << PERFCTL0_RWOFOEN_SHIFT); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << TEST2_4_TESTAUDINIT_SHIFT) | - (0xd << TEST2_4_TESTAUDINC_SHIFT)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - TEST2_3_TESTCNT_MASK | (0x1 << TEST2_3_TESTAUDPAT_SHIFT), - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); + dramc_engine2_setpat(chn, test_pat); }
-static void dramc_engine2_check_complete(u8 chn) +static void dramc_engine2_check_complete(u8 chn, u8 status) { + u32 loop = 0; /* In some case test engine finished but the complete signal late come, * system will wait very long time. Hence, we set a timeout here. * After system receive complete signal or wait until time out * it will return, the caller will check compare result to verify * whether engine success. */ - if (!wait_us(10000, read32(&ch[chn].nao.testrpt) & 0x1)) - dramc_dbg("MEASURE_A timeout\n"); + while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) { + if (loop++ > 100) + dramc_dbg("MEASURE_A timeout\n"); + } +} + +static void dramc_engine2_compare(u8 chn, enum dram_te_op wr) +{ + u8 rank_status = ((read32(&ch[chn].ao.test2_3) & 0xf) == 1) ? 3 : 1; + + if (wr == TE_OP_WRITE_READ_CHECK) { + dramc_engine2_check_complete(chn, rank_status); + + clrbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT)); + udelay(1); + setbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT)); + } + + dramc_engine2_check_complete(chn, rank_status); }
static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) @@ -478,26 +618,21 @@ if (wr == TE_OP_READ_CHECK) { clrbits_le32(&ch[chn].ao.test2_4, 0x1 << TEST2_4_TESTAUDMODE_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), + 0x1 << TEST2_3_TEST2R_SHIFT); } else if (wr == TE_OP_WRITE_READ_CHECK) { clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2W_SHIFT); - - dramc_engine2_check_complete(chn); - clrbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT)); - udelay(1); }
- /* Do read test */ - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT), - 0x1 << TEST2_3_TEST2R_SHIFT); - - dramc_engine2_check_complete(chn); + dramc_engine2_compare(chn, wr);
udelay(1); result = read32(&ch[chn].nao.cmp_err); @@ -654,7 +789,8 @@
dramc_rx_dqs_isi_pulse_cg_switch(chn, true);
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, ((u32) best_coarse_tune2t[0] << SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | ((u32) best_coarse_tune2t[1] << @@ -663,7 +799,8 @@ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | ((u32) best_coarse_tune2t_p1[1] << SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, ((u32) best_coarse_tune0p5t[0] << SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | ((u32) best_coarse_tune0p5t[1] << @@ -703,7 +840,8 @@ } }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, ((u32) best_coarse_rodt[0] << SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | ((u32) best_coarse_rodt[1] << @@ -712,7 +850,8 @@ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | ((u32) best_coarse_rodt_p1[1] << SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, ((u32) best_coarse_0p5t_rodt[0] << SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | ((u32) best_coarse_0p5t_rodt[1] << @@ -726,10 +865,12 @@ best_fine_tune[0] | (best_fine_tune[1] << 8)); }
-static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) +extern u8 MR01Value[FSP_MAX]; +static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u32 freq_group) { u8 dqs; - const u8 mr1_value = 0x56; + u32 fsp = ( (freq_group == LP4X_DDR1600) ? FSP_0: FSP_1); + const u8 mr1_value = MR01Value[fsp]; u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}; u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], min_fine_tune[DQS_NUMBER]; @@ -760,8 +901,16 @@ dramc_rx_dqs_gating_cal_pre(chn, rank);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x23, true); + dramc_engine2_init(chn, rank, TEST2_1_CAL, 0xaa000023, true);
+ if (freq_group == LP4X_DDR1600) + coarse_start = 18; + else if (freq_group == LP4X_DDR3200) + coarse_start = 25; + else if (freq_group == LP4X_DDR3600) + coarse_start = 21; + + coarse_end = coarse_start + 12; dramc_dbg("[Gating]\n"); for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune += DQS_GW_COARSE_STEP) { @@ -787,42 +936,46 @@ value - (dly_coarse_large_rodt_p1 << 3); }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + ((u32) dly_coarse_large << 0) | + ((u32) dly_coarse_large << 8) | + ((u32) dly_coarse_large << 16) | + ((u32) dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | + (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | + (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + ((u32) dly_coarse_0p5t << 0) | + ((u32) dly_coarse_0p5t << 8) | + ((u32) dly_coarse_0p5t << 16) | + ((u32) dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | + (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | + (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | + (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | + (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | + (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | + (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | + (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | + (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | + (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | + (dly_coarse_0p5t_rodt_p1 << 28));
for (u8 dly_fine_xt = DQS_GW_FINE_START; dly_fine_xt < DQS_GW_FINE_END; @@ -933,8 +1086,7 @@ u16 temp_value = 0;
for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT); + clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); @@ -951,14 +1103,17 @@ (mr15_golden_value << 8) | mr20_golden_value); }
-static u32 dramc_rd_dqc_run(u8 chn) +static u32 dramc_rx_rd_dqc_run(u8 chn) { + u32 loop = 0; setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT);
- if (!wait_us(100, read32(&ch[chn].nao.spcmdresp) & - (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT))) - dramc_dbg("[RDDQC] resp fail (time out)\n"); + while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & + (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT))) { + if (loop++ > 10) + dramc_dbg("[RDDQC] resp fail (time out)\n"); + }
u32 result = read32(&ch[chn].nao.rdqc_cmp); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); @@ -974,18 +1129,16 @@
static void dramc_rx_vref_enable(u8 chn) { - setbits_le32(&ch[chn].phy.b[0].dq[5], - 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT); - setbits_le32(&ch[chn].phy.b[1].dq[5], - 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT); + setbits_le32(&ch[chn].phy.b[0].dq[5], 0x1 << 16); + setbits_le32(&ch[chn].phy.b[1].dq[5], 0x1 << 16); }
static void dramc_set_rx_vref(u8 chn, u8 value) { for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK, - value << SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT); + 0x3f, value << 0); + dramc_dbg("set rx vref :%d\n", value); }
static void dramc_set_tx_vref(u8 chn, u8 rank, u8 value) @@ -1004,17 +1157,18 @@ static void dramc_transfer_dly_tune( u8 chn, u32 dly, struct tx_dly_tune *dly_tune) { - u16 tmp_val; + u8 tune = 3; + u16 tmp;
dly_tune->fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1);
- tmp_val = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; - dly_tune->coarse_tune_small = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large = tmp_val >> 3; + tmp = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; + dly_tune->coarse_tune_small = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large = tmp >> tune;
- tmp_val -= 4; - dly_tune->coarse_tune_small_oen = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large_oen = tmp_val >> 3; + tmp -= 4; + dly_tune->coarse_tune_small_oen = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large_oen = tmp >> tune; }
static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) @@ -1052,48 +1206,53 @@ } }
-static void dramc_set_tx_dly_factor(u8 chn, u8 rank, - enum CAL_TYPE type, u32 val) +static void dramc_set_tx_dly_factor(u8 chn, u8 rk, + enum CAL_TYPE type, u32 dly) { struct tx_dly_tune dly_tune = {0}; - u32 coarse_tune_large = 0, coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0, coarse_tune_small_oen = 0; + u32 dly_large = 0, dly_large_oen = 0, dly_small = 0, dly_small_oen = 0; + u32 tmp = 0xff;
- dramc_transfer_dly_tune(chn, val, &dly_tune); + dramc_transfer_dly_tune(chn, dly, &dly_tune);
for (u8 i = 0; i < 4; i++) { - coarse_tune_large += dly_tune.coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dly_tune.coarse_tune_large_oen << (i * 4); - coarse_tune_small += dly_tune.coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dly_tune.coarse_tune_small_oen << (i * 4); + dly_large += dly_tune.coarse_tune_large << (i * 4); + dly_large_oen += dly_tune.coarse_tune_large_oen << (i * 4); + dly_small += dly_tune.coarse_tune_small << (i * 4); + dly_small_oen += dly_tune.coarse_tune_small_oen << (i * 4); } + if (type == TX_WIN_DQ_DQM) dramc_dbg("%3d |%d %d %2d | [0]", - val, dly_tune.coarse_tune_large, + dly, dly_tune.coarse_tune_large, dly_tune.coarse_tune_small, dly_tune.fine_tune);
- if (type != TX_WIN_DQ_DQM && type != TX_WIN_DQ_ONLY) - return; + if (tmp != dly_large) { + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], + 0x77777777, dly_small | (dly_small_oen << 16)); + }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + if (type == TX_WIN_DQ_DQM) { + /* Large coarse_tune setting */ + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], + 0x77777777, dly_small | (dly_small_oen << 16)); + } + tmp = dly_large; + }
- if (type == TX_WIN_DQ_DQM) { - /* Large coarse_tune setting */ - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - /* Fine_tune delay setting */ + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], + FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + } + if (type == TX_WIN_DQ_DQM) { + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); } } @@ -1101,22 +1260,33 @@ static u32 dramc_get_smallest_dqs_dly( u8 chn, u8 rank, const struct sdram_params *params) { - u32 min_dly = 0xffff; + u8 mck = 3; + u32 min_dly = 0xffff, virtual_delay = 0; + u32 tx_dly = read32(&ch[chn].ao.shu[0].selph_dqs0); + u32 dly = read32(&ch[chn].ao.shu[0].selph_dqs1);
- for (size_t i = 0; i < DQS_NUMBER; i++) - min_dly = MIN(min_dly, params->wr_level[chn][rank][i]); + for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { + virtual_delay = (((((tx_dly >> (dqs << 2)) & 0x7) << mck) + ((dly >> (dqs << 2)) & 0x7)) << 5) + + params->wr_level[chn][rank][dqs]; + min_dly = MIN(min_dly, virtual_delay); + }
- return DQS_DELAY + min_dly + 40; + return min_dly; }
static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, - u16 *pre_cal, s16 *begin, s16 *end, + u32 freq_group, u16 *pre_cal, s16 *begin, s16 *end, const struct sdram_params *params) { u16 pre_dq_dly; switch (type) { case RX_WIN_RD_DQC: - *begin = FIRST_DQS_DELAY; + if (freq_group == LP4X_DDR1600) + *begin = -48; + else if (freq_group >= LP4X_DDR3200) + *begin = -26; + else + *begin = -64; *end = MAX_RX_DQDLY_TAPS; break;
@@ -1138,22 +1308,22 @@ break; } } -static int dramc_check_dqdqs_win( +static int dramc_check_rx_dqdqs_win( struct dqdqs_perbit_dly *p, s16 dly_pass, s16 last_step, bool fail, bool is_dq) { s16 best_pass_win; - struct perbit_dly *dly = is_dq ? &p->dqdly : &p->dqsdly; + struct perbit_dly *dly = (is_dq ? &p->dqdly : &p->dqsdly);
- if (!fail && dly->first == -1) + if (!fail && dly->first == PASS_RANGE_NA) dly->first = dly_pass;
- if (!fail && dly->last == -2 && dly_pass == last_step) + if (!fail && dly->last == PASS_RANGE_NA && dly_pass == last_step) dly->last = dly_pass; - else if (fail && dly->first != -1 && dly->last == -2) + else if (fail && dly->first != PASS_RANGE_NA && dly->last == PASS_RANGE_NA) dly->last = dly_pass - 1;
- if (dly->last == -2) + if (dly->last == PASS_RANGE_NA) return 0;
int pass_win = dly->last - dly->first; @@ -1163,8 +1333,8 @@ dly->best_first = dly->first; } /* Clear to find the next pass range if it has */ - dly->first = -1; - dly->last = -2; + dly->first = PASS_RANGE_NA; + dly->last = PASS_RANGE_NA;
return pass_win; } @@ -1210,7 +1380,7 @@ return true;
break; - case TX_DQ_DQS_MOVE_DQ_ONLY: + case RX_WIN_RD_DQC: for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { win_size = delay[bit].dqdly.best_last - delay[bit].dqdly.best_first + 1; @@ -1218,8 +1388,10 @@ win_size_sum += win_size; }
- if (win_size_sum > vref_dly->max_win - && vref_dly->min_win >= min_win_size_vref) { + dramc_dbg(" %s win_size_sum:%d, max_win:%d, vref_dly->min_win :%d, min_win_size_vref:%d \n", + __func__, win_size_sum, vref_dly->max_win, vref_dly->min_win, min_win_size_vref); + if ((win_size_sum > vref_dly->max_win) + && (vref_dly->min_win >= min_win_size_vref)) { min_win_size_vref = vref_dly->min_win; dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); } @@ -1246,7 +1418,7 @@ byte_delay_prop->max_center = win_center; }
-static void dramc_set_rx_dly(u8 chn, u8 rank, s32 dly) +static void dramc_set_rx_dqdqs_dly(u8 chn, u8 rank, s32 dly) { if (dly <= 0) { /* Hold time calibration */ @@ -1262,12 +1434,10 @@ }
static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, - struct per_byte_dly *tx_perbyte_dly, u16 dq_precal_result[]) + struct per_byte_dly *tx_perbyte_dly, u16 dq_precal_dly[]) { - u32 coarse_tune_large = 0; - u32 coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0; - u32 coarse_tune_small_oen = 0; + u32 dq_large = 0, dq_large_oen = 0, dq_small = 0, dq_small_oen = 0; + u32 dqm_large = 0, dqm_large_oen = 0, dqm_small = 0, dqm_small_oen = 0; u16 dq_oen[DQS_NUMBER] = {0}, dqm_oen[DQS_NUMBER] = {0}; struct tx_dly_tune dqdly_tune[DQS_NUMBER] = {0}; struct tx_dly_tune dqmdly_tune[DQS_NUMBER] = {0}; @@ -1275,15 +1445,18 @@ for (size_t i = 0; i < DQS_NUMBER; i++) { dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly, &dqdly_tune[i]); - dramc_transfer_dly_tune(chn, dq_precal_result[i], + dramc_transfer_dly_tune(chn, dq_precal_dly[i], &dqmdly_tune[i]);
- coarse_tune_large += dqdly_tune[i].coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dqdly_tune[i].coarse_tune_large_oen << (i * 4); - coarse_tune_small += dqdly_tune[i].coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dqdly_tune[i].coarse_tune_small_oen << (i * 4); + dq_large += dqdly_tune[i].coarse_tune_large << (i * 4); + dq_large_oen += dqdly_tune[i].coarse_tune_large_oen << (i * 4); + dq_small += dqdly_tune[i].coarse_tune_small << (i * 4); + dq_small_oen += dqdly_tune[i].coarse_tune_small_oen << (i * 4); + + dqm_large += dqmdly_tune[i].coarse_tune_large << (i * 4); + dqm_large_oen += dqmdly_tune[i].coarse_tune_large_oen << (i * 4); + dqm_small += dqmdly_tune[i].coarse_tune_small << (i * 4); + dqm_small_oen += dqmdly_tune[i].coarse_tune_small_oen << (i * 4);
dq_oen[i] = (dqdly_tune[i].coarse_tune_large_oen << 3) + (dqdly_tune[i].coarse_tune_small_oen << 5) + @@ -1294,24 +1467,21 @@ }
for (size_t rank = rank_start; rank < RANK_MAX; rank++) { - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - } + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + 0x77777777, dq_large | (dq_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, dq_small| (dq_small_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + 0x77777777, dqm_large | (dqm_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, dqm_small | (dqm_small_oen << 16));
- for (size_t rank = rank_start; rank < RANK_MAX; rank++) for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, - (dqdly_tune[b].fine_tune << - FINE_TUNE_DQ_SHIFT) | - (dqmdly_tune[b].fine_tune << - FINE_TUNE_DQM_SHIFT)); + (dqdly_tune[b].fine_tune << 8) | + (dqmdly_tune[b].fine_tune << 16)); + } }
static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, @@ -1344,8 +1514,8 @@ { u8 fail = 0, hold, setup;
- hold = p->dqsdly.best_last - p->dqsdly.best_first + 1; setup = p->dqdly.best_last - p->dqdly.best_first + 1; + hold = p->dqsdly.best_last - p->dqsdly.best_first + 1;
if (hold > setup) { p->dqdly.best = 0; @@ -1370,8 +1540,8 @@ } }
- dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", bit, setup, - hold, setup + hold, p->dqdly.best, p->dqsdly.best); + dramc_dbg("bit#%d: dq win=%d, dqs win=%d total win=%d (%d~%d)\n", + bit, setup, hold, setup + hold, p->dqdly.best_first, p->dqdly.best_last);
return fail; } @@ -1379,7 +1549,7 @@ static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, s32 dly) { if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) - dramc_set_rx_dly(chn, rank, dly); + dramc_set_rx_dqdqs_dly(chn, rank, dly); else dramc_set_tx_dly_factor(chn, rank, type, dly); } @@ -1490,40 +1660,19 @@ *vref_end = TX_VREF_END; } else { *vref_scan_en = 0; + *vref_begin = 0; + *vref_end = 1; } }
-static void dramc_engine2_setpat(u8 chn, bool test_pat) -{ - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); - - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << 8) | (0xd << 0) | (0x1 << 14)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); -} - static u32 dram_k_perbit(u8 chn, enum CAL_TYPE type) { u32 err_value;
if (type == RX_WIN_RD_DQC) { - err_value = dramc_rd_dqc_run(chn); + err_value = dramc_rx_rd_dqc_run(chn); + } else if (type == RX_WIN_TEST_ENG) { + err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); } else { dramc_engine2_setpat(chn, true); err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); @@ -1533,7 +1682,7 @@ return err_value; }
-static u8 dramc_window_perbit_cal(u8 chn, u8 rank, +static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u32 freq_group, enum CAL_TYPE type, const struct sdram_params *params) { u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1; @@ -1570,7 +1719,7 @@ dramc_rd_dqc_init(chn, rank); } else { dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); }
vref_dly.max_win = 0; @@ -1599,7 +1748,7 @@ RX_DQ, FIRST_DQ_DELAY); }
- dramc_get_dly_range(chn, rank, type, dq_precal_result, + dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, &dly_begin, &dly_end, params); for (dly = dly_begin; dly < dly_end; dly += dly_step) { dramc_set_dqdqs_dly(chn, rank, type, dly); @@ -1624,7 +1773,7 @@
/* pass window bigger than 7, consider as real pass window */ - if (dramc_check_dqdqs_win(&(dq_perbit_dly[bit]), + if (dramc_check_rx_dqdqs_win(&(dq_perbit_dly[bit]), dly_pass, last_step, fail, flag) > 7) finish_bit |= (1 << bit); @@ -1643,9 +1792,11 @@ }
for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win(%d ~ %d)\n", bit, + dramc_dbg("Dq[%zd] win width %d(%d ~ %d)\n", bit, + dq_perbit_dly[bit].dqdly.best_last - dq_perbit_dly[bit].dqdly.best_first, dq_perbit_dly[bit].dqdly.best_first, dq_perbit_dly[bit].dqdly.best_last); + dramc_dbg(" \n");
if (dramk_calc_best_vref(type, vref, &vref_dly, dq_perbit_dly)) break; @@ -1696,7 +1847,7 @@ chn, rank, best_step);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false);
for (datlat = 12; datlat < DATLAT_TAP_NUMBER; datlat++) { dramc_dle_factor_handler(chn, datlat); @@ -1801,7 +1952,8 @@ best_coarse_tune2t_p1[rank][dqs]); }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, (best_coarse_tune2t[rank][0] << 0) | (best_coarse_tune2t[rank][1] << 8) | (best_coarse_tune2t_p1[rank][0] << 4) | @@ -1837,7 +1989,7 @@ read_dqsinctl, rankinctl_root, xrtr2r); }
-void dramc_calibrate_all_channels(const struct sdram_params *pams) +void dramc_calibrate_all_channels(const struct sdram_params *pams, u32 freq_group) { u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -1847,12 +1999,12 @@ dramc_cmd_bus_training(chn, rk, pams); dramc_write_leveling(chn, rk, pams->wr_level); dramc_auto_refresh_switch(chn, true); - dramc_rx_dqs_gating_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); + dramc_rx_dqs_gating_cal(chn, rk, freq_group); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_RD_DQC, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_DQM, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_ONLY, pams); rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams); }
dramc_rx_dqs_gating_post_process(chn); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 937d06d..27d80e8 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -19,6 +19,8 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h>
+u32 freqTbl[LP4X_DDRFREQ_MAX] = {DDR_FREQ_1600, DDR_FREQ_3200, DDR_FREQ_3600}; + struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { [CHANNEL_A] = { @@ -268,18 +270,34 @@ setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31); }
-static void dramc_ac_timing_optimize(void) +typedef struct { + u8 u1TRFC : 8; + u8 u1TRFRC_05T : 1; + u16 u2TXREFCNT : 10; +} optimizeACTime; + +static void dramc_ac_timing_optimize(u32 freq_group) +{ + optimizeACTime tRFCab_Opt[LP4X_DDRFREQ_MAX] = + { + {.u1TRFC = 44, .u1TRFRC_05T = 0, .u2TXREFCNT = 62}, //DDR1600 + {.u1TRFC = 100, .u1TRFRC_05T = 0, .u2TXREFCNT = 119}, //DDR3200 + {.u1TRFC = 118, .u1TRFRC_05T = 1, .u2TXREFCNT = 138}, //DDR3600 + }; + dramc_dbg("%s with freq:%d: u1TRFC %d, u2TXREFCNT:%d\n", __func__, freq_group, + tRFCab_Opt[freq_group].u1TRFC, tRFCab_Opt[freq_group].u2TXREFCNT); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); + 0xff << 16, tRFCab_Opt[freq_group].u1TRFC << 16); clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, tRFCab_Opt[freq_group].u2TXREFCNT << 0); } }
-static void init_dram(const struct sdram_params *params) +static void init_dram(const struct sdram_params *params, u32 freq_group) { global_option_init(params); emi_init(params); @@ -288,7 +306,8 @@ dramc_init_pre_settings(); dramc_sw_impedance(params);
- dramc_init(); + dramc_init(params, freq_group); + dramc_apply_config_before_calibration(); emi_init2(params); }
@@ -301,17 +320,27 @@ clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); }
-static void do_calib(const struct sdram_params *params) +static void do_calib(const struct sdram_params *params, u32 freq_group) { - dramc_apply_config_before_calibration(); - dramc_calibrate_all_channels(params); - dramc_ac_timing_optimize(); + dramc_show("Start K freq group:%d\n", freqTbl[freq_group]); + dramc_calibrate_all_channels(params, freq_group); + dramc_ac_timing_optimize(freq_group); + dramc_show("%s K freq group:%d finish!\n", __func__, freqTbl[freq_group]); +} + +static void after_calib(void) +{ dramc_apply_config_after_calibration(); dramc_runtime_config(); }
void mt_set_emi(const struct sdram_params *params) { - init_dram(params); - do_calib(params); + u32 freq_group = LP4X_DDR3600; + dramc_show("%s with: freq_sel %d,\n", __func__, freq_group); + + init_dram(params, freq_group); + + do_calib(params, freq_group); + after_calib(); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 23b5cf0..815d586 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -38,6 +38,21 @@ #define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a
+enum +{ + LP4X_DDR1600, + LP4X_DDR3200, + LP4X_DDR3600, + LP4X_DDRFREQ_MAX, +}; + +enum +{ + DDR_FREQ_1600 = 1600, + DDR_FREQ_3200 = 3200, + DDR_FREQ_3600 = 3600, +}; + enum dram_te_op { TE_OP_WRITE_READ_CHECK = 0, TE_OP_READ_CHECK @@ -114,19 +129,21 @@ SELPH_DQS1 = (DQS_DELAY_0P5T << 0) | (DQS_DELAY_0P5T << 4) | (DQS_DELAY_0P5T << 8) | (DQS_DELAY_0P5T << 12) | (DQS_OEN_DELAY_0P5T << 16) | (DQS_OEN_DELAY_0P5T << 20) | - (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28) + (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28), };
void dramc_get_rank_size(u64 *dram_rank_size); void dramc_runtime_config(void); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); -void dramc_init(void); +void dramc_init(const struct sdram_params *params, u32 freq_group); void dramc_sw_impedance(const struct sdram_params *params); void dramc_apply_config_before_calibration(void); void dramc_apply_config_after_calibration(void); -void dramc_calibrate_all_channels(const struct sdram_params *params); +void dramc_calibrate_all_channels(const struct sdram_params *pams, u32 freq_group); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); +void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); +void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off);
#endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index f0720a7..40138e8 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -945,12 +945,15 @@ };
enum { + MISC_STATUSA_SREF_STATE = 16, MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000, };
enum { SPCMDRESP_RDDQC_RESPONSE_SHIFT = 7, + SPCMDRESP_ZQLAT_RESPONSE_SHIFT = 6, + SPCMDRESP_ZQC_RESPONSE_SHIFT = 4, };
enum { @@ -974,6 +977,8 @@ };
enum { + MRS_MPCRK_SHIFT = 28, + MRS_MPCRK_MASK = 0x30000000, MRS_MRSRK_SHIFT = 24, MRS_MRSRK_MASK = 0x03000000, MRS_MRSMA_SHIFT = 8, @@ -986,6 +991,8 @@ SPCMD_DQSGCNTRST_SHIFT = 9, SPCMD_DQSGCNTEN_SHIFT = 8, SPCMD_RDDQCEN_SHIFT = 7, + SPCMD_ZQLATEN_SHIFT = 6, + SPCMD_ZQCEN_SHIFT = 4, SPCMD_MRWEN_SHIFT = 0, };
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 1:
(186 comments)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1721: static void dramc_duty_set_dqs_delay(u8 chn, s8* s_dqsDelay) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1724: s8 dqsDelay ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1728: dqsDelay = s_dqsDelay[dqs] ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1867: MR01Value[FSP_0] |= (0x5 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1868: MR01Value[FSP_1] |= (0x5 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1873: MR01Value[FSP_0] |= (0x5 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1874: MR01Value[FSP_1] |= (0x5 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1879: MR01Value[FSP_0] |= (0x6 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1880: MR01Value[FSP_1] |= (0x6 << 4); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1893: dramc_dbg("%s CH%u RK%u, freq:%d\n", __func__, chn, rank, freqTbl[freq_group]); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1937: if (operate_fsp == FSP_0) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1937: if (operate_fsp == FSP_0) suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1941: else that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1941: else suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1941: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1968: { open brace '{' following struct go on the same line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1969: u8 dqsinctl; please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1996: u8 twtr_05T; please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2000: u8 tfaw_05T; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2001: u8 trrd_05T; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2002: u8 twr_05T; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2003: u8 tras_05T; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2004: u8 trpab_05T; please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2011: u8 trc_05T; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2012: u8 r_dmcatrain_intv; please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2014: u8 r_dmfspchg_prdcnt; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2015: u8 ckeprd; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2016: u8 ckelckcnt; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2017: u8 zqlat2; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2018: }ACTime_T; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2021: { that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2059: .tras = 8, .tras_05T = 1, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2059: .tras = 8, .tras_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2060: .trp = 5, .trp_05T = 1, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2060: .trp = 5, .trp_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2061: .trpab = 1, .trpab_05T = 0, code indent should use tabs where possible
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2062: .trc = 16, .trc_05T = 1, please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2064: .trfcpb = 44, .trfcpb_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2064: .trfcpb = 44, .trfcpb_05T = 0, please, no spaces at the start of a line
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https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2066: .trtp = 2, .trtp_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2067: .trcd = 6, .trcd_05T = 1, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2067: .trcd = 6, .trcd_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2068: .twr = 12, .twr_05T = 1, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2068: .twr = 12, .twr_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2069: .twtr = 7, .twtr_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2069: .twtr = 7, .twtr_05T = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2070: .trrd = 2, .trrd_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2070: .trrd = 2, .trrd_05T = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2071: .tfaw = 7, .tfaw_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2071: .tfaw = 7, .tfaw_05T = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2072: .trtw_ODT_on = 7, .trtw_ODT_on_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2072: .trtw_ODT_on = 7, .trtw_ODT_on_05T = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2073: .refcnt = 97, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2073: .refcnt = 97, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2074: .refcnt_fr_clk = 101, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2074: .refcnt_fr_clk = 101, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2075: .txrefcnt = 119, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2075: .txrefcnt = 119, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2076: .tzqcs = 34, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2076: .tzqcs = 34, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2077: .xrtw2w = 5, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2077: .xrtw2w = 5, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2078: .xrtw2r = 3, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2078: .xrtw2r = 3, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2079: .xrtr2w = 6, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2079: .xrtr2w = 6, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2080: .xrtr2r = 9, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2080: .xrtr2r = 9, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2081: .r_dmcatrain_intv = 11, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2081: .r_dmcatrain_intv = 11, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2082: .r_dmmrw_intv = 0xf, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2082: .r_dmmrw_intv = 0xf, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2083: .r_dmfspchg_prdcnt = 100, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2083: .r_dmfspchg_prdcnt = 100, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2084: .trtpd = 11, .trtpd_05T = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2084: .trtpd = 11, .trtpd_05T = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2085: .twtpd = 12, .twtpd_05T = 1, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2085: .twtpd = 12, .twtpd_05T = 1, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2086: .tmrr2w_ODT_on = 10, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2086: .tmrr2w_ODT_on = 10, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2087: .ckeprd = 2, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2087: .ckeprd = 2, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2088: .ckelckcnt = 0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2088: .ckelckcnt = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2089: .zqlat2 = 12, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2089: .zqlat2 = 12, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2090: .dqsinctl = 4, .datlat = 15 code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2090: .dqsinctl = 4, .datlat = 15 please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2117: .r_dmmrw_intv = 0xf, //Berson: LP3/4 both use this field -> Formula may change, set to 0xF for now line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2202: u1ROOT = 0; u1TXRANKINCTL=0; u1TXDLY=1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2202: u1ROOT = 0; u1TXRANKINCTL=0; u1TXDLY=1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2208: u1TXRANKINCTL=1; u1TXDLY=2; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2208: u1TXRANKINCTL=1; u1TXDLY=2; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2238: (twtr_05T << 25) | (trtw_ODT_on_05T << 24) | (twtpd_05T << 16) | (trtpd_05T << 15) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 2239: (tfaw_05T << 13) | (trrd_05T << 12) | (twr_05T << 10) | (tras_05T << 9) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 152: 0x7 << 4 | 0x1 << 7 | 0x3 <<0, need consistent spacing around '<<' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 165: tmp_2t = (read32(reg_1) >> shift) & DQ_DIV_MASK ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 265: if (wrlevel_dq_delay >= 0x40) { suspect code indent for conditional statements (16, 32)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 872: u32 fsp = ( (freq_group == LP4X_DDR1600) ? FSP_0: FSP_1); spaces required around that ':' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 872: u32 fsp = ( (freq_group == LP4X_DDR1600) ? FSP_0: FSP_1); space prohibited after that open parenthesis '('
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 942: ((u32) dly_coarse_large << 8) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 942: ((u32) dly_coarse_large << 8) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 942: ((u32) dly_coarse_large << 8) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 944: ((u32) dly_coarse_large << 24) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 944: ((u32) dly_coarse_large << 24) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 944: ((u32) dly_coarse_large << 24) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 952: ((u32) dly_coarse_0p5t << 8) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 952: ((u32) dly_coarse_0p5t << 8) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 952: ((u32) dly_coarse_0p5t << 8) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 954: ((u32) dly_coarse_0p5t << 24) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 954: ((u32) dly_coarse_0p5t << 24) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 954: ((u32) dly_coarse_0p5t << 24) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 962: (dly_coarse_large_rodt << 8) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 962: (dly_coarse_large_rodt << 8) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 962: (dly_coarse_large_rodt << 8) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 964: (dly_coarse_large_rodt << 24) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 964: (dly_coarse_large_rodt << 24) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 964: (dly_coarse_large_rodt << 24) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 972: (dly_coarse_0p5t_rodt << 8) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 972: (dly_coarse_0p5t_rodt << 8) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 972: (dly_coarse_0p5t_rodt << 8) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 974: (dly_coarse_0p5t_rodt << 24) | code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 974: (dly_coarse_0p5t_rodt << 24) | please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 974: (dly_coarse_0p5t_rodt << 24) | please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1112: while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & suspect code indent for conditional statements (8, 17)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1114: if (loop++ > 10) Statements should start on a tabstop
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1269: virtual_delay = (((((tx_dly >> (dqs << 2)) & 0x7) << mck) + ((dly >> (dqs << 2)) & 0x7)) << 5) + line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1391: dramc_dbg(" %s win_size_sum:%d, max_win:%d, vref_dly->min_win :%d, min_win_size_vref:%d \n", unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1392: __func__, win_size_sum, vref_dly->max_win, vref_dly->min_win, min_win_size_vref); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1473: 0x77777777, dq_small| (dq_small_oen << 16)); need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1796: dq_perbit_dly[bit].dqdly.best_last - dq_perbit_dly[bit].dqdly.best_first, line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/dra... PS1, Line 1799: dramc_dbg(" \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/emi... PS1, Line 274: { open brace '{' following struct go on the same line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/emi... PS1, Line 283: { that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 42: { open brace '{' following enum go on the same line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 43: LP4X_DDR1600, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 44: LP4X_DDR3200, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 45: LP4X_DDR3600, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 46: LP4X_DDRFREQ_MAX, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 50: { open brace '{' following enum go on the same line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 51: DDR_FREQ_1600 = 1600, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 52: DDR_FREQ_3200 = 3200, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/1/src/soc/mediatek/mt8183/inc... PS1, Line 53: DDR_FREQ_3600 = 3600, please, no spaces at the start of a line
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG@9 PS1, Line 9: DDR frequency fix at 3600Mbps Please elaborate. For a diffstat of over 10 lines (here over a thousand), an elaborate commit message is required.
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG@16 PS1, Line 16: Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Please move this directly above the Signed-off-by line.
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#2).
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: support DDR frequency 3600Mbps
DDR frequency fix at 3600Mbps
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform Signed-off-by: Huayang Duan huayang.duan@mediatek.com
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,676 insertions(+), 262 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 2:
(21 comments)
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1728: dqsDelay = s_dqsDelay[dqs] ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1893: dramc_dbg("%s CH%u RK%u, freq:%d\n", __func__, chn, rank, freqTbl[freq_group]); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1937: if (operate_fsp == FSP_0) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1937: if (operate_fsp == FSP_0) suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1941: else that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1941: else suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1941: else else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1969: { open brace '{' following struct go on the same line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 2022: { that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 2118: .r_dmmrw_intv = 0xf, //Berson: LP3/4 both use this field -> Formula may change, set to 0xF for now line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 2131: { open brace '{' following struct go on the same line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 2239: (twtr_05T << 25) | (trtw_ODT_on_05T << 24) | (twtpd_05T << 16) | (trtpd_05T << 15) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 2240: (tfaw_05T << 13) | (trrd_05T << 12) | (twr_05T << 10) | (tras_05T << 9) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 152: (0x7 << 4) |(0x1 << 7) |(0x3 << 0), need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 152: (0x7 << 4) |(0x1 << 7) |(0x3 << 0), need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1269: virtual_delay = (((((tx_dly >> (dqs << 2)) & 0x7) << mck) + ((dly >> (dqs << 2)) & 0x7)) << 5) + line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1391: dramc_dbg(" %s win_size_sum:%d, max_win:%d, vref_dly->min_win :%d, min_win_size_vref:%d \n", unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1392: __func__, win_size_sum, vref_dly->max_win, vref_dly->min_win, min_win_size_vref); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/dra... PS2, Line 1796: dq_perbit_dly[bit].dqdly.best_last - dq_perbit_dly[bit].dqdly.best_first, line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/emi... PS2, Line 274: { open brace '{' following struct go on the same line
https://review.coreboot.org/c/coreboot/+/34332/2/src/soc/mediatek/mt8183/emi... PS2, Line 283: { that open brace { should be on the previous line
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#3).
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Due to the init setting of freq 3600Mbps not same as current 3200Mbps, so add a new init-sequence for 3600Mbps. Due to the Mode register value need used at RX gating calibration, so need implement the mode register init function, and use the global variable to same the mode register value.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,629 insertions(+), 262 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1890: dramc_dbg("mode reg init, CH%u RK%u, freq:%d\n", chn, rank, freqTbl[freq_group]); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1903: MR13Value = (1 <<4) | (1<<3); need consistent spacing around '<<' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1933: if (operate_fsp == FSP_0) { suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1933: if (operate_fsp == FSP_0) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1935: } else { suspect code indent for conditional statements (24, 28)
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 2109: .r_dmmrw_intv = 0xf, //Berson: LP3/4 both use this field -> Formula may change, set to 0xF for now line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1239: virtual_delay = (((((tx_dly >> (dqs << 2)) & 0x7) << mck) + \ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1240: ((dly >> (dqs << 2)) & 0x7)) << 5) + params->wr_level[chn][rank][dqs]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1361: dramc_dbg("win_size_sum:%d, max_win:%d, vref_dly->min_win :%d, min_win_size_vref:%d \n", unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/34332/3/src/soc/mediatek/mt8183/dra... PS3, Line 1766: dq_perbit_dly[bit].dqdly.best_last - dq_perbit_dly[bit].dqdly.best_first, line over 96 characters
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#4).
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Due to the init setting of freq 3600Mbps not same as current 3200Mbps, so add a new init-sequence for 3600Mbps. Due to the Mode register value need used at RX gating calibration, so need implement the mode register init function, and use the global variable to same the mode register value.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,640 insertions(+), 268 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... PS4, Line 363: if (get_dram_type() == DRAM_TYPE_DISCRETE) { braces {} are not necessary for any arm of this statement
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... PS4, Line 363: extra space
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#5).
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Due to the init setting of freq 3600Mbps not same as current 3200Mbps, so add a new init-sequence for 3600Mbps. Due to the Mode register value need used at RX gating calibration, so need implement the mode register init function, and use the global variable to same the mode register value.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,639 insertions(+), 268 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/5
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 5:
I see an assertion error with this patch. Could you check the log with DEBUG_DRAM here? https://pastebin.com/htgc4hev
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 5:
Patch Set 5:
I see an assertion error with this patch. Could you check the log with DEBUG_DRAM here? https://pastebin.com/htgc4hev
How many devices be tested by apply this 3600Mbps patch? Does this device can bootup pass not have this patch?
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: support DDR frequency 3600Mbps ......................................................................
Patch Set 5:
Patch Set 5:
Patch Set 5:
I see an assertion error with this patch. Could you check the log with DEBUG_DRAM here? https://pastebin.com/htgc4hev
How many devices be tested by apply this 3600Mbps patch? Does this device can bootup pass not have this patch?
Yes, the device can boot into kernel without this patch. Currently only tried one Krane Proto device.
Yu-Ping Wu has uploaded a new patch set (#6) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,640 insertions(+), 268 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/6
Yu-Ping Wu has uploaded a new patch set (#7) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 1,642 insertions(+), 268 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/7
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/7//COMMIT_MSG@8 PS7, Line 8: hungte: I think the commit message needs to be revised but I don't know how.
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#8).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,786 insertions(+), 1,880 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 8:
(82 comments)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 58: }else if (freq_group == LP4X_DDR3200) { space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 68: if (freq_group == LP4X_DDR1600) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 88: (0x0 << 31) | (0x0 << 30) | (0x6 << 20) | (0x9 << 16 )| space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 97: (0x1 << 31) | (0x1 << 30) | (0x7 << 20 )| (0x7 << 16 )| need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 97: (0x1 << 31) | (0x1 << 30) | (0x7 << 20 )| (0x7 << 16 )| space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 546: if (freq_group == LP4X_DDR1600) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 554: (midpi_cap_sel << 9) | (0x1 << 10)| (0x3 << 17)| (lp3_sel << 20)); need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 554: (midpi_cap_sel << 9) | (0x1 << 10)| (0x3 << 17)| (lp3_sel << 20)); need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 676: resp = (read32(&ch[chn].nao.spcmdresp) >>4) & 0x1; need consistent spacing around '>>' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 846: clrsetbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29) |(0x1 << 31), need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 847: (0x0 << 29) |(0x1 << 31)); need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 851: int value = ( (rank == 0) ? 0x1a : 0x1e); space prohibited after that open parenthesis '('
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 901: setbits_le32(&ch[0].ao.shu[0].odtctrl,(0x1 << 0) | (0x1 << 30)| (0x1 << 31)); space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 901: setbits_le32(&ch[0].ao.shu[0].odtctrl,(0x1 << 0) | (0x1 << 30)| (0x1 << 31)); need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 913: int value = ( (rank == 0) ? 0x19 : 0x1f); space prohibited after that open parenthesis '('
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1309: clrsetbits_le32(&ch[0].ao.perfctl0, (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1376: setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) |(0x1 << 13)); need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1385: update_initial_settings(freq_group); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1385: update_initial_settings(freq_group); please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1385: update_initial_settings(freq_group); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1731: clrsetbits_le32(&ch[chn].ao.shu[0].conf[2], (0xff << 8), (r_dmfspchg_prdcnt << 8)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 223: (freq_group == LP4X_DDR1600)|| (freq_group == LP4X_DDR2400) )) spaces required around that '||' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 223: (freq_group == LP4X_DDR1600)|| (freq_group == LP4X_DDR2400) )) space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 645: }else { space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 820: u8 dqs, fsp, freqDiv= 4; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1002: dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp] ); space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1097: } else if (fine_tune > TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP -10) { need consistent spacing around '-' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1300: win_size = delay[bit].best_last -delay[bit].best_first ; need consistent spacing around '-' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1300: win_size = delay[bit].best_last -delay[bit].best_first ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1333: win_size = delay[bit].best_last -delay[bit].best_first ; need consistent spacing around '-' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1333: win_size = delay[bit].best_last -delay[bit].best_first ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1344: if ((min_winsize > *win_min_max) || ((min_winsize == *win_min_max) && (tmp_win_sum > vref_dly->max_win_sum))) { line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1396: dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly, adjust_center, &dqdly_tune[i]); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1410: (dqdly_tune[i].coarse_tune_small_oen << 5) + dqdly_tune[i].fine_tune; line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1433: write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], byte_dly_cell[byte]); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1438: (dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1439: (dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1441: clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1442: (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1443: clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1444: (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1445: clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1446: (dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1470: value = (dly[index + 1].best_dqdly << 24) | (dly[index + 1].best_dqdly << 16) | line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1533: chn, rank, byte, center_dly[byte].min_center, center_dly[byte].max_center); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1538: center_dly[byte].final_dly = (center_dly[byte].min_center + center_dly[byte].max_center) >> 1; line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1547: tune_diff = vref_dly[index].win_center - center_dly[byte].min_center; line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1548: dq_delay_cell[index] = ((tune_diff * 100000000) / (freq / 2 * 64)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1577: dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte] ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1580: perbit_dly[bit].best_dqdly = dqsdly_byte[byte] + perbit_dly[bit].win_center; line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1596: if (fsp == FSP_0) { braces {} are not necessary for any arm of this statement
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1730: dramc_dbg("all bits window found, early break! delay=0x%x\n", dly); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1738: win_perbit[bit].best_last -win_perbit[bit].best_first); need consistent spacing around '-' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1768: u8 StartEXT2=0, StartEXT3=0, LastEXT2=0, LastEXT3=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1768: u8 StartEXT2=0, StartEXT3=0, LastEXT2=0, LastEXT3=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1768: u8 StartEXT2=0, StartEXT3=0, LastEXT2=0, LastEXT3=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1768: u8 StartEXT2=0, StartEXT3=0, LastEXT2=0, LastEXT3=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1781: if(val >= 24) space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1783: else if(val >= 18) space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1787: (0x1 << 28)| (0x1 << 27) | (0x1 << 26), need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1788: (0x1 << 31) | (0x1 << 30)| (StartEXT2 << 29) | need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1789: (LastEXT2 << 28)| (StartEXT3 << 27) | (LastEXT3 << 26)); need consistent spacing around '|' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1795: u32 datlat, begin = 0, first = 0 ,sum = 0, best_step; space prohibited before that ',' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1795: u32 datlat, begin = 0, first = 0 ,sum = 0, best_step; space required after that ',' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1842: clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | 0x1 << 3 , space prohibited before that ',' (ctx:WxE)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1863: if ((freq_group == LP4X_DDR3200) ||(freq_group == LP4X_DDR3600) ) spaces required around that '||' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1863: if ((freq_group == LP4X_DDR3200) ||(freq_group == LP4X_DDR3600) ) space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1920: clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl,0xf, read_dqsinctl << 0); space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1921: clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) |(0xf << 20) | (0xf << 24) | (0xf ), line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1921: clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) |(0xf << 20) | (0xf << 24) | (0xf ), need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1921: clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) |(0xf << 20) | (0xf << 24) | (0xf ), space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/dra... PS8, Line 1922: (read_dqsinctl << 28) | (rankinctl_root << 20) | (rankinctl_root << 24) | (rankinctl_root)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/emi... PS8, Line 344: while (loop < loop_cnt) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/emi... PS8, Line 347: for (u8 *addr = _dram; addr < (u8*)0x100000000; addr+=0x40000000) { "(foo*)" should be "(foo *)"
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/emi... PS8, Line 347: for (u8 *addr = _dram; addr < (u8*)0x100000000; addr+=0x40000000) { spaces required around that '+=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h:
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 20: { open brace '{' following enum go on the same line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 21: DRAM_DFS_SHUFFLE_1 = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 22: DRAM_DFS_SHUFFLE_2, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 23: DRAM_DFS_SHUFFLE_3, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 24: DRAM_DFS_SHUFFLE_MAX please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 108: DLL_MASTER = 0, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/34332/8/src/soc/mediatek/mt8183/inc... PS8, Line 109: DLL_SLAVE, please, no spaces at the start of a line
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/7//COMMIT_MSG@8 PS7, Line 8:
hungte: I think the commit message needs to be revised but I don't know how.
Ack
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#9).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,797 insertions(+), 1,880 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 9:
(19 comments)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... PS9, Line 68: if (freq_group == LP4X_DDR1600) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... PS9, Line 87: (0x0 << 31) | (0x0 << 30) | (0x6 << 20) | (0x9 << 16 ) | space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... PS9, Line 96: (0x1 << 31) | (0x1 << 30) | (0x7 << 20 ) | (0x7 << 16 ) | space prohibited before that close parenthesis ')'
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... PS9, Line 1853: clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | 0x1 << 3 , space prohibited before that ',' (ctx:WxE)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/dra... PS9, Line 1933: (0xf << 28) |(0xf << 20) | (0xf << 24) | 0xf, need consistent spacing around '|' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 23: <<<<<<< HEAD spaces required around that '<' (ctx:OxW)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 24: ======= spaces required around that '==' (ctx:ExO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 24: ======= spaces required around that '==' (ctx:OxO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 24: ======= spaces required around that '==' (ctx:OxO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 24: ======= spaces required around that '=' (ctx:OxE)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 27: >>>>>>> 68cd2f807b... mediatek/mt8183: Support DDR frequency 3600Mbps spaces required around that '>' (ctx:OxW)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 27: >>>>>>> 68cd2f807b... mediatek/mt8183: Support DDR frequency 3600Mbps spaces required around that ':' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 340: <<<<<<< HEAD spaces required around that '<' (ctx:OxW)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 341: ======= spaces required around that '==' (ctx:ExO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 341: ======= spaces required around that '==' (ctx:OxO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 341: ======= spaces required around that '==' (ctx:OxO)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 341: ======= spaces required around that '=' (ctx:OxE)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 365: >>>>>>> 68cd2f807b... mediatek/mt8183: Support DDR frequency 3600Mbps spaces required around that '>' (ctx:OxW)
https://review.coreboot.org/c/coreboot/+/34332/9/src/soc/mediatek/mt8183/emi... PS9, Line 365: >>>>>>> 68cd2f807b... mediatek/mt8183: Support DDR frequency 3600Mbps spaces required around that ':' (ctx:VxW)
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#10).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,790 insertions(+), 1,880 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/10
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/10/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/10/src/soc/mediatek/mt8183/dr... PS10, Line 95: (0x1 << 31) | (0x1 << 30) | (0x7 << 20 ) | (0x7 << 16) | space prohibited before that close parenthesis ')'
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#11).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Since the init setting of freq 3600Mbps is not same as current 3200Mbps, a new init-sequence for 3600Mbps is added. Also, since the mode register value needs to be used at RX gating calibration, we need to implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,765 insertions(+), 1,921 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/11
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#12).
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
mediatek/mt8183: Support DDR frequency 3600Mbps
Add DDR frequency 3600Mbps for EMCP DDR, and fix DDR frequency at 3600Mbps. Using the source code to implement the init setting instead of hard init-sequence. Also, since the mode register value needs to be used at RX gating calibration, we implement the mode register init function and use the global variable to make the mode register value the same.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 7 files changed, 2,759 insertions(+), 1,927 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/12
Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12: Code-Review+2
DRAM 3600M patch verify PASS at 3 KUKUI platforms
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
Hi Huayang, this looks like a huge patch with multiple fixed merged together. Can you split this into smaller chunks, and each fixing one topic at a time? I think it may include:
- Add mode register init function - Replace hard-coded init sequence by complete logic - Add DDR frequency 3600Mbps for eMCP DDR - Fix DDR frequency at 3600Mbps
(although I'm not sure why you said you have to add first then fix)
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
(13 comments)
also, I think there are lots of white-space-only changes, to combine those function calls into a larger line > 80 cols.
I think we don't want to mix styling, especially white-space only changes, with CLs that really changing code logic. Please revert those, or have them done in a separate CL (although I don't think those should be merged since they're breaking the col 80 role).
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 177: (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); exceed col 80
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 248: 0x3fffff << 10); no need to fix white space here - keep this unchanged (as two lines).
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 251: 0x3fffff << 10, 0x2 << 10); should be no white space change here
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 314: , 0x8060033e | (0x40 << (en ? 0x1 : 0))); : write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033f | (0x40 << (en ? 0x1 : 0))); : write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033e | (0x40 << (en ? 0x1 : 0))); : : clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, (en ? 0 : 0x3) << 26); exceed col 80
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 349: < 14, (on ? 0x3 : 0) << 14); no white space only changes.
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 21: : u32 freqTbl[LP4X_DDRFREQ_MAX] = {DDR_FREQ_1600, DDR_FREQ_3200, DDR_FREQ_3600, DDR_FREQ_2400}; u32 frequency_table[LP4X_DDRFREQ_MAX] = { [LP4X_DDRFREQ_1600] = DDR_FREQ_1600, [LP4X_DDRFREQ_3200] = DDR_FREQ_3200, [LP4X_DDRFREQ_3600] = DDR_FREQ_3600, [LP4X_DDRFREQ_2400] = DDR_FREQ_2400, };
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 37: typedef we don't do typedef according to kernel coding style. just use struct.
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 282: //DDR1600 use the [LP4X_DDRFREQ_1600]= {.rfc...} style so there's no need to comment (and match ordering).
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 287: freq_group, exceed col 80
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 57: (CONFIG(MT8183_DRAM_EMCP)) if CONFIG(MT8183_DRAM_EMCP)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 58: (LP4X_DDR3600) no need to add () if this is single value.
Meanwhile, from your current implementation there's only emi.c needs to decide this value, so I'd more prefer to not do the header definition; instead you should put the logic in .c file, i.e.,
u32 current_freq;
if (CONFIG(MT8183_DRAM_EMCP)) current_freq = LP4X_DDR3600; else current_freq = LP4X_DDR3200;
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 59: LP4X_MIDDLE_FREQ not used anywhere?
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 60: LP4X_LOW_FREQ not used anywhere?
Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 177: (0x1 << 29) | (0x0 << 4) | (0x1 << 0));
exceed col 80
I see the check-patch script only complain line over 96 characters, so to reduce the line count，move some 2-line to 1-line
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 59: LP4X_MIDDLE_FREQ
not used anywhere?
DVFS feature will using 3 freq, that is low,middle,high freq.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 177: (0x1 << 29) | (0x0 << 4) | (0x1 << 0));
I see the check-patch script only complain line over 96 characters, so to reduce the line count，move […]
I think "line count of existing file" is not important; in fact it's more important for "line count of diff in one patchset for review".
There're some ongoing discussion in columns of line for Coreboot. Some suggested using clangformat, but the docs.coreboot.org is still saying 80, "unless exceeding 80 columns significantly increases readability and does not hide information".
No matter what, we should not put these white-space changes into a change with real functional changes. So please remove/revert them. You can create one dedicated patchset for fixing all whitespace if you really think that's the better format.
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 59: LP4X_MIDDLE_FREQ
DVFS feature will using 3 freq, that is low,middle,high freq.
Got it. In that case, Can we put them into an array, and let some code (in emi.c?) select the right array? Unless if the high/middle/low will be used in many different places and can't be parsed as arguments.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
(9 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 82: if (u1CA_DLL_Mode[chn] == DLL_MASTER) { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x0 << 31) | (0x0 << 30) | (0x6 << 20) | (0x9 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x1 << 2) | (0x0 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x1 << 7); : } else { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x1 << 31) | (0x1 << 30) | (0x7 << 20) | (0x7 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x0 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x0 << 2) | (0x1 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x0 << 7); : } it's really not easy to figure out the difference in such long list. I'd recommend setting them to different vars, for example
int is_dll_master = (u1CA_DLL_Mode[chn] == DLL_MASTER);
clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], 01x << 31 | 0x1 << 30 | 0xf << 20 | 0xf << 16 | 0xf << 12 | 0x1 << 10 | 0x1 << 9 | 0x1 << 4, !is_master << 31 | !is_master << 30 | (is_master ? 7 : 6) << 20 | (is_master ? 9 : 7) << 16, ....
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 248: (0x1 << 4 no need to quote as a simple arg, i.e.
setbits_le32(..., 0x1 << 4);
Same to all similar calls.
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 265: delat do you want to say delta?
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 268: else so for other groups, delat = 0?
I think you can add en else to make it clear.
else delat = 0;
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 271: ((freq_group == LP4X_DDR3200) || (freq_group == LP4X_DDR3600)) No need to quote.
if (a == b || c == d)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 309: ((freq == LP4X_DDR1600) || (freq == LP4X_DDR2400)) ? FSP_0 : FSP_1; if (freq == ... || freq == ...) return FSP_0; else return FSP_1;
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 651: #define TIME_OUT_CNT 100 //100us since only one function use it, put this into dramc_zq_calibration as
const u32 TIMEOUT_COUNT = 100;
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 672: do { : resp = (read32(&ch[chn].nao.spcmdresp) >> 4) & 0x1; : u4TimeCnt--; : udelay(1); : } while ((resp == 0) && (u4TimeCnt > 0)); : : if (u4TimeCnt == 0) { : dramc_dbg("ZQCAL Start fail (time out)\n"); : return 1; : } use wait_us macro?
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 688: do { : resp = (read32(&ch[chn].nao.spcmdresp) >> 6) & 0x1; : u4TimeCnt--; : udelay(1); : } while ((resp == 0) && (u4TimeCnt > 0)); : : if (u4TimeCnt == 0) { : dramc_dbg("ZQCAL Latch fail (time out)\n"); : return 1; : } use wait_us macro?
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support DDR frequency 3600Mbps ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 309: ((freq == LP4X_DDR1600) || (freq == LP4X_DDR2400)) ? FSP_0 : FSP_1;
if (freq == ... || freq == ...) […]
Out of curiosity, is this coreboot's convention or just for readability?
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#13).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup. Now can support DRAM frequency 1600Mbps, 2400Mbps, 3200Mbps, 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 907 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/13
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 430: MR13Value &= ~(0x1<<3); Add space around "<<".
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 660: pass_byte_cnt |= (1<<dqs); Add space around "<<".
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1600: dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte]; Extra space before "=".
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1895: best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7; Extra space after "=".
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#14).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup. Now can support DRAM frequency 1600Mbps, 2400Mbps, 3200Mbps, 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 911 insertions(+), 776 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/14
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#15).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup. Now can support DRAM frequency 1600Mbps, 2400Mbps, 3200Mbps, 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 921 insertions(+), 783 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/15
Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 15:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 82: if (u1CA_DLL_Mode[chn] == DLL_MASTER) { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x0 << 31) | (0x0 << 30) | (0x6 << 20) | (0x9 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x1 << 2) | (0x0 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x1 << 7); : } else { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x1 << 31) | (0x1 << 30) | (0x7 << 20) | (0x7 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x0 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x0 << 2) | (0x1 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x0 << 7); : }
it's really not easy to figure out the difference in such long list. […]
I think current style was easy to debug and read.
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 177: (0x1 << 29) | (0x0 << 4) | (0x1 << 0));
I think "line count of existing file" is not important; in fact it's more important for "line count […]
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 430: MR13Value &= ~(0x1<<3);
Add space around "<<".
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 660: pass_byte_cnt |= (1<<dqs);
Add space around "<<".
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 825: static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params)
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1600: dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte];
Extra space before "=".
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1895: best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7;
Extra space after "=".
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 15:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 309: ((freq == LP4X_DDR1600) || (freq == LP4X_DDR2400)) ? FSP_0 : FSP_1;
Out of curiosity, is this coreboot's convention or just for readability?
I'd say readability.
If you want to return as one line I'm probably fine, but ((a == b) || (c == d)) should be avoided. since the operator precedence is clear we can simply do (a == b || c == d).
And next - the code below wasdoing
if (operate_fsp = FSP1) ... else ...
So I'd say for consistency, if-else may be better in this case.
I'd more prefer to use ?: in very simple, inline params.
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 639: TIMEOUT_CNT TIMEOUT_US = 100
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 658: while (!wait_us(1, read32(&ch[chn].nao.spcmdresp) & (0x1 << 4)) && (time_cnt > 0)) : time_cnt--; : : if (time_cnt == 0) { : dramc_dbg("ZQCAL Start fail (time out)\n"); : return 1; : } if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4) { dramc_dbg("ZQCAL Start fail (time out)\n"); return 1; }
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 671: : while (!wait_us(1, read32(&ch[chn].nao.spcmdresp) & (0x1 << 6)) && (time_cnt > 0)) : time_cnt--; : : if (time_cnt == 0) { : dramc_dbg("ZQCAL Latch fail (time out)\n"); : return 1; : } if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) { dramc_dbg("ZACAL latch fail (timeout)\n"); return 1; }
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 15:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG@9 PS1, Line 9: DDR frequency fix at 3600Mbps
Please elaborate. […]
Done
https://review.coreboot.org/c/coreboot/+/34332/1//COMMIT_MSG@16 PS1, Line 16: Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207
Please move this directly above the Signed-off-by line.
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 147: tmp_0p5t = (((read32(reg_0) >> shift) & DQ_DIV_MASK) & (~(1 << DQ_DIV_SHIFT))); Don't need the outermost parentheses.
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 551: while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) { What does it mean to compare the return value of wait_us() to status?
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 870: coarse_start = 22; Consider ``` else coarse_start = 26; ``` for readability.
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1053: Extra space
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1098: adjust_cneter adjust_center
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/4/src/soc/mediatek/mt8183/emi... PS4, Line 363:
extra space
Done
Yu-Ping Wu has uploaded a new patch set (#16) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 6 files changed, 930 insertions(+), 792 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/16
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/16/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/16/src/soc/mediatek/mt8183/dr... PS16, Line 701: dqs, dly_coarse_large_cnt[dqs], dly_coarse_0p5t_cnt[dqs], dly_fine_tune_cnt[dqs]); line over 96 characters
Yu-Ping Wu has uploaded a new patch set (#17) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 6 files changed, 935 insertions(+), 796 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/17
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/16/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/16/src/soc/mediatek/mt8183/dr... PS16, Line 701: dqs, dly_coarse_large_cnt[dqs], dly_coarse_0p5t_cnt[dqs], dly_fine_tune_cnt[dqs]);
line over 96 characters
Done
Yu-Ping Wu has uploaded a new patch set (#18) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 6 files changed, 937 insertions(+), 798 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/18
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 18:
(15 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 271: ((freq_group == LP4X_DDR3200) || (freq_group == LP4X_DDR3600))
No need to quote. […]
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 309: ((freq == LP4X_DDR1600) || (freq == LP4X_DDR2400)) ? FSP_0 : FSP_1;
I'd say readability. […]
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 651: #define TIME_OUT_CNT 100 //100us
since only one function use it, put this into dramc_zq_calibration as […]
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 672: do { : resp = (read32(&ch[chn].nao.spcmdresp) >> 4) & 0x1; : u4TimeCnt--; : udelay(1); : } while ((resp == 0) && (u4TimeCnt > 0)); : : if (u4TimeCnt == 0) { : dramc_dbg("ZQCAL Start fail (time out)\n"); : return 1; : }
use wait_us macro?
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 688: do { : resp = (read32(&ch[chn].nao.spcmdresp) >> 6) & 0x1; : u4TimeCnt--; : udelay(1); : } while ((resp == 0) && (u4TimeCnt > 0)); : : if (u4TimeCnt == 0) { : dramc_dbg("ZQCAL Latch fail (time out)\n"); : return 1; : }
use wait_us macro?
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 248: 0x3fffff << 10);
no need to fix white space here - keep this unchanged (as two lines).
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 251: 0x3fffff << 10, 0x2 << 10);
should be no white space change here
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 314: , 0x8060033e | (0x40 << (en ? 0x1 : 0))); : write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033f | (0x40 << (en ? 0x1 : 0))); : write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033e | (0x40 << (en ? 0x1 : 0))); : : clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, (en ? 0 : 0x3) << 26);
exceed col 80
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 349: < 14, (on ? 0x3 : 0) << 14);
no white space only changes.
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 21: : u32 freqTbl[LP4X_DDRFREQ_MAX] = {DDR_FREQ_1600, DDR_FREQ_3200, DDR_FREQ_3600, DDR_FREQ_2400};
u32 frequency_table[LP4X_DDRFREQ_MAX] = { […]
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 37: typedef
we don't do typedef according to kernel coding style. just use struct.
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 282: //DDR1600
use the [LP4X_DDRFREQ_1600]= {.rfc...} style so there's no need to comment (and match ordering).
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/em... PS12, Line 287: freq_group,
exceed col 80
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 57: (CONFIG(MT8183_DRAM_EMCP))
if CONFIG(MT8183_DRAM_EMCP)
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 58: (LP4X_DDR3600)
no need to add () if this is single value. […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/18//COMMIT_MSG@11 PS18, Line 11: For such a big diffstat you should elaborate more on the implementation.
https://review.coreboot.org/c/coreboot/+/34332/18/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/18/src/soc/mediatek/mt8183/dr... PS18, Line 159: (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); Format changes should be in separate commits.
Yu-Ping Wu has uploaded a new patch set (#19) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 920 insertions(+), 777 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/19
Yu-Ping Wu has uploaded a new patch set (#20) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 911 insertions(+), 766 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/20
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/18/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/18/src/soc/mediatek/mt8183/dr... PS18, Line 159: (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
Format changes should be in separate commits.
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 265: delat
do you want to say delta?
Done
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 268: else
so for other groups, delat = 0? […]
Done
Yu-Ping Wu has uploaded a new patch set (#21) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 914 insertions(+), 766 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/21
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 21:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 639: TIMEOUT_CNT
TIMEOUT_US = 100
Done
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 658: while (!wait_us(1, read32(&ch[chn].nao.spcmdresp) & (0x1 << 4)) && (time_cnt > 0)) : time_cnt--; : : if (time_cnt == 0) { : dramc_dbg("ZQCAL Start fail (time out)\n"); : return 1; : }
if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4) { […]
Done
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 671: : while (!wait_us(1, read32(&ch[chn].nao.spcmdresp) & (0x1 << 6)) && (time_cnt > 0)) : time_cnt--; : : if (time_cnt == 0) { : dramc_dbg("ZQCAL Latch fail (time out)\n"); : return 1; : }
if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) { […]
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 870: coarse_start = 22;
Consider […]
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1053:
Extra space
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1098: adjust_cneter
adjust_center
Done
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/15/src/soc/mediatek/mt8183/dr... PS15, Line 701: dqs, dly_coarse_large_cnt[dqs], dly_coarse_0p5t_cnt[dqs], dly_fine_tune_cnt[dqs]);
line over 96 characters
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 248: (0x1 << 4
no need to quote as a simple arg, i.e. […]
Done
Yu-Ping Wu has uploaded a new patch set (#23) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 914 insertions(+), 766 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/23
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 22:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1600: dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte];
Done
Ack
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 1895: best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7;
Done
Ack
Yu-Ping Wu has uploaded a new patch set (#24) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 912 insertions(+), 765 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/24
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 24:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 147: tmp_0p5t = (((read32(reg_0) >> shift) & DQ_DIV_MASK) & (~(1 << DQ_DIV_SHIFT)));
Don't need the outermost parentheses.
Done
https://review.coreboot.org/c/coreboot/+/34332/13/src/soc/mediatek/mt8183/dr... PS13, Line 551: while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) {
What does it mean to compare the return value of wait_us() to status?
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 24:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... PS24, Line 148: tmp_0p5t = ((read32(reg_0) >> shift) & DQ_DIV_MASK) & trailing whitespace
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... PS24, Line 552: if (!wait_us(100, read32(&ch[chn].nao.testrpt) & status)) { braces {} are not necessary for single statement blocks
Yu-Ping Wu has uploaded a new patch set (#25) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 911 insertions(+), 765 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/25
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... PS25, Line 148: tmp_0p5t = ((read32(reg_0) >> shift) & DQ_DIV_MASK) & trailing whitespace
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 25:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... PS24, Line 148: tmp_0p5t = ((read32(reg_0) >> shift) & DQ_DIV_MASK) &
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/34332/24/src/soc/mediatek/mt8183/dr... PS24, Line 552: if (!wait_us(100, read32(&ch[chn].nao.testrpt) & status)) {
braces {} are not necessary for single statement blocks
Done
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... PS25, Line 552: if (!wait_us(100, read32(&ch[chn].nao.testrpt) & status)) @huayang Is this what you want?
Yu-Ping Wu has uploaded a new patch set (#26) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 911 insertions(+), 765 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/26
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#27).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 918 insertions(+), 770 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/27
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#28).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 917 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/28
Yu-Ping Wu has uploaded a new patch set (#29) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 918 insertions(+), 774 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/29
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 60: LP4X_LOW_FREQ
not used anywhere?
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 29:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/dr... PS12, Line 82: if (u1CA_DLL_Mode[chn] == DLL_MASTER) { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x0 << 31) | (0x0 << 30) | (0x6 << 20) | (0x9 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x1 << 2) | (0x0 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x1 << 7); : } else { : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], : (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | : (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), : (0x1 << 31) | (0x1 << 30) | (0x7 << 20) | (0x7 << 16) | : (0x8 << 12) | (0x1 << 10) | (0x1 << 9) | (0x0 << 4)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], : (0x1 << 2) | (0x1 << 0), (0x0 << 2) | (0x1 << 0)); : clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, 0x0 << 7); : }
I think current style was easy to debug and read.
Ack
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/25/src/soc/mediatek/mt8183/dr... PS25, Line 552: if (!wait_us(100, read32(&ch[chn].nao.testrpt) & status))
@huayang Is this what you want?
Ack
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... PS29, Line 553: while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) { What do you mean to compare the return value with status?
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... File src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/34332/12/src/soc/mediatek/mt8183/in... PS12, Line 59: LP4X_MIDDLE_FREQ
Got it. In that case, Can we put them into an array, and let some code (in emi. […]
Done. See https://review.coreboot.org/c/coreboot/+/34990/14..15.
Yu-Ping Wu has uploaded a new patch set (#30) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test pass on EMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 918 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/30
Yu-Ping Wu has uploaded a new patch set (#33) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 918 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/33
Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34332/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34332/18//COMMIT_MSG@11 PS18, Line 11:
For such a big diffstat you should elaborate more on the implementation.
Done
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... PS29, Line 553: while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) {
What do you mean to compare the return value with status?
the test result must same as the expect value(the rank status), otherwise wait until timeout.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/29/src/soc/mediatek/mt8183/dr... PS29, Line 553: while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) {
the test result must same as the expect value(the rank status), otherwise wait until timeout.
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 35:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 149: (~(1 << DQ_DIV_SHIFT)) ~(1 << DQ_DIV_SHIRT)
(no need to quote again)
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 176: (byte * 4) byte * 4
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 223: (rank == RANK_0) rank == RANK_0
Yu-Ping Wu has uploaded a new patch set (#36) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 922 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/36
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 36:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34332/36/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/36/src/soc/mediatek/mt8183/dr... PS36, Line 1255: else if (freq_group == LP4X_DDR3200 || trailing whitespace
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 36:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 108: ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7)); @hungte Could we write "cke_on << 6" directly? What's the convention in coreboot?
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 149: (~(1 << DQ_DIV_SHIFT))
~(1 << DQ_DIV_SHIRT) […]
Done
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 176: (byte * 4)
byte * 4
Done
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 223: (rank == RANK_0)
rank == RANK_0
Done
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 875: if (freq_group == LP4X_DDR1600) : coarse_start = 18; : else if (freq_group == LP4X_DDR2400) : coarse_start = 25; : else if (freq_group == LP4X_DDR3200) : coarse_start = 25; : else if (freq_group == LP4X_DDR3600) : coarse_start = 21; : else : coarse_start = 26; Change to switch statement.
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 1254: else : *begin = -64; I don't see how this could possibly happen because the above conditions seem to include all the cases.
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 1545: clock_rate = 800; @hungte There are lots of switch statements for freq_group like this. Should we change this to die()? Or it is expected to have more frequency groups in the future?
Yu-Ping Wu has uploaded a new patch set (#37) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 922 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/37
Yu-Ping Wu has uploaded a new patch set (#39) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 926 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/39
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 39:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 108: ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7));
@hungte […]
I'm ok either way.
For C++ bool is properly defined to be true=1, false=0. For C99 the stdbool has same definition. For other, that is undefined.
Coreboot is not really using stdbool, but there was plan to migrate so it's fine.
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 1254: else : *begin = -64;
I don't see how this could possibly happen because the above conditions seem to include all the case […]
Ack
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 1545: clock_rate = 800;
@hungte […]
I think we should really die on things we can't be sure if that will work or not.
https://review.coreboot.org/c/coreboot/+/34332/38/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/38/src/soc/mediatek/mt8183/dr... PS38, Line 1258: else : *begin = -64; this implies not a well-supported case that maybe we should probably die or also warn something.
Yu-Ping Wu has uploaded a new patch set (#40) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 943 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/40
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 40:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 108: ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7));
I'm ok either way. […]
I'm not going to change it then.
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 875: if (freq_group == LP4X_DDR1600) : coarse_start = 18; : else if (freq_group == LP4X_DDR2400) : coarse_start = 25; : else if (freq_group == LP4X_DDR3200) : coarse_start = 25; : else if (freq_group == LP4X_DDR3600) : coarse_start = 21; : else : coarse_start = 26;
Change to switch statement.
Done
https://review.coreboot.org/c/coreboot/+/34332/35/src/soc/mediatek/mt8183/dr... PS35, Line 1545: clock_rate = 800;
I think we should really die on things we can't be sure if that will work or not.
Done
https://review.coreboot.org/c/coreboot/+/34332/38/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/34332/38/src/soc/mediatek/mt8183/dr... PS38, Line 1258: else : *begin = -64;
this implies not a well-supported case that maybe we should probably die or also warn something.
Done
Yu-Ping Wu has uploaded a new patch set (#41) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 941 insertions(+), 773 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/41
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 41: Code-Review+2
Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Sj Huang, Hung-Te Lin, Huayang Duan, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34332
to look at the new patch set (#42).
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 955 insertions(+), 776 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/42
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 42: Code-Review+2
Yu-Ping Wu has uploaded a new patch set (#43) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 955 insertions(+), 776 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/34332/43
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 43: Code-Review+2
inherit CR+2, the latest changes are coding style only (and for the better)
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
mediatek/mt8183: Support more DRAM frequency bootup
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps.
BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform
Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan huayang.duan@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h 5 files changed, 955 insertions(+), 776 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index bf8bf0e..a194d7a 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -223,7 +223,7 @@
static void transfer_pll_to_spm_control(void) { - u8 shu_lev = (read32(&ch[0].ao.shustatus) & 0x00000006) >> 1; + u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3;
clrsetbits_le32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), @@ -264,6 +264,7 @@
for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { + clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), @@ -286,7 +287,6 @@ clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
for (u8 b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[9], @@ -294,6 +294,7 @@ (0x1 << 28) | (0x0 << 24)); setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); } + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); @@ -346,16 +347,12 @@ setbits_le32(&ch[chn].ao.impcal, 0x1 << 19); } setbits_le32(&ch[0].ao.impcal, 0x1 << 14); - setbits_le32(&ch[1].ao.refctrl0, 0x1 << 2); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 3); + setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); }
static void dramc_phy_low_power_enable(void) { - u32 broadcast_bak = dramc_get_broadcast(); - dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { for (size_t b = 0; b < 2; b++) { clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2], @@ -367,8 +364,6 @@ } write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); write32(&ch[1].phy.ca_dll_fine_tune[3], 0x3a000); - - dramc_set_broadcast(broadcast_bak); }
static void dramc_dummy_read_for_tracking_enable(u8 chn) @@ -384,8 +379,8 @@ for (size_t r = 0; r < 2; r++) { clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), - (0x7fff << 0) | (0x3f0 << 17)); - setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + (0xffff << 0) | (0x3f0 << 17)); + clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); }
clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); @@ -433,7 +428,7 @@ clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29);
transfer_pll_to_spm_control(); - setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25); + setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
/* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 97926535..fcc3b14 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -14,6 +14,7 @@ */
#include <assert.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/emi.h> @@ -23,24 +24,23 @@
enum { RX_VREF_BEGIN = 0, - RX_VREF_END = 12, + RX_VREF_END = 31, RX_VREF_STEP = 1, - TX_VREF_BEGIN = 8, - TX_VREF_END = 18, + TX_VREF_BEGIN = 0, + TX_VREF_END = 50, TX_VREF_STEP = 2, };
enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -16, + FIRST_DQS_DELAY = -48, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, };
-enum { - GATING_START = 26, - GATING_END = GATING_START + 24, -}; +#define WRITE_LEVELING_MOVD_DQS 1 +#define TEST2_1_CAL 0x55000000 +#define TEST2_2_CAL 0xaa000400
enum CAL_TYPE { RX_WIN_RD_DQC = 0, @@ -55,21 +55,19 @@ RX_DQS, };
-struct dqdqs_perbit_dly { - struct perbit_dly { - s16 first; - s16 last; - s16 best_first; - s16 best_last; - s16 best; - } dqdly, dqsdly; +struct win_perbit_dly { + s16 first_pass; + s16 last_pass; + s16 best_first; + s16 best_last; + s16 best_dqdly; + s16 win_center; };
struct vref_perbit_dly { - u8 vref; - u16 max_win; - u16 min_win; - struct dqdqs_perbit_dly perbit_dly[DQ_DATA_WIDTH]; + u8 best_vref; + u16 max_win_sum; + struct win_perbit_dly perbit_dly[DQ_DATA_WIDTH]; };
struct tx_dly_tune { @@ -86,6 +84,9 @@ u16 final_dly; };
+extern u8 MR01Value[FSP_MAX]; +extern u8 MR13Value; + static void dramc_auto_refresh_switch(u8 chn, bool option) { clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, @@ -102,10 +103,10 @@ } }
-void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off) +void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) { clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), - ((fix_on ? 1 : 0) << 6) | ((fix_off ? 1 : 0) << 7)); + ((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7)); }
void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) @@ -124,13 +125,15 @@ ;
clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); - setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); + write32(&ch[chn].ao.ckectrl, ckectrl_bak); + dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); }
static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; + dramc_dbg("Mode reg write rank%d MR%d = 0x%x\n", rank, mr_idx, value);
clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); @@ -138,26 +141,113 @@ clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); }
-static void dramc_write_leveling(u8 chn, u8 rank, +static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_tune) +{ + s32 sum; + u32 tmp_0p5t, tmp_2t; + + tmp_0p5t = ((read32(reg_0) >> shift) & DQ_DIV_MASK) & + ~(1 << DQ_DIV_SHIFT); + tmp_2t = (read32(reg_1) >> shift) & DQ_DIV_MASK; + + sum = (tmp_2t << DQ_DIV_SHIFT) + tmp_0p5t + shift_coarse_tune; + + if (sum < 0) { + tmp_0p5t = 0; + tmp_2t = 0; + } else { + tmp_2t = sum >> DQ_DIV_SHIFT; + tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT); + } + + clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); + clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); +} + +static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, byte * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dqs_oen(u8 chn, u8 byte, + s8 shift_coarse_tune) +{ + move_dramc_delay(&ch[chn].ao.shu[0].selph_dqs1, + &ch[chn].ao.shu[0].selph_dqs0, byte * 4 + OEN_SHIFT, shift_coarse_tune); +} + +static void move_dramc_tx_dq(u8 chn, u8 rank, u8 byte, s8 shift_coarse_tune) +{ + /* DQM0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], byte * 4, shift_coarse_tune); + + /* DQ0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], byte * 4, shift_coarse_tune); +} + +static void move_dramc_tx_dq_oen(u8 chn, u8 rank, + u8 byte, s8 shift_coarse_tune) +{ + /* DQM_OEN_0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + &ch[chn].ao.shu[0].rk[rank].selph_dq[1], + byte * 4 + OEN_SHIFT, shift_coarse_tune); + + /* DQ_OEN_0 */ + move_dramc_delay(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + &ch[chn].ao.shu[0].rk[rank].selph_dq[0], + byte * 4 + OEN_SHIFT, shift_coarse_tune); +} + +static void write_leveling_move_dqs_instead_of_clk(u8 chn) +{ + dramc_dbg("%s do ch:%d k\n", __func__, chn); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + move_dramc_tx_dqs(chn, byte, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dqs_oen(chn, byte, -WRITE_LEVELING_MOVD_DQS); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + move_dramc_tx_dq(chn, rk, byte, -WRITE_LEVELING_MOVD_DQS); + move_dramc_tx_dq_oen(chn, rk, byte, -WRITE_LEVELING_MOVD_DQS); + } + } +} + +static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) { + dramc_auto_refresh_switch(chn, false); + + if (rank == RANK_0 && (freq_group == LP4X_DDR3600 || + freq_group == LP4X_DDR1600 || + freq_group == LP4X_DDR2400)) + write_leveling_move_dqs_instead_of_clk(chn); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0);
- for (size_t i = 0; i < DQS_NUMBER; i++) { - s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; - assert(wrlevel_dq_delay < 0x40); + for (size_t byte = 0; byte < DQS_NUMBER; byte++) { + u32 wrlevel_dq_delay = wr_level[chn][rank][byte] + 0x10; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_PBYTE_MASK, + wr_level[chn][rank][byte] << FINE_TUNE_PBYTE_SHIFT); + if (wrlevel_dq_delay >= 0x40) { + wrlevel_dq_delay -= 0x40; + move_dramc_tx_dq(chn, rank, byte, 2); + move_dramc_tx_dq_oen(chn, rank, byte, 2); + }
- clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], - FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | - FINE_TUNE_DQ_MASK, - (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], + FINE_TUNE_DQM_MASK | FINE_TUNE_DQ_MASK, (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); } }
-static void dramc_cmd_bus_training(u8 chn, u8 rank, +static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { u32 cbt_cs, mr12_value; @@ -209,9 +299,6 @@
void dramc_enable_phy_dcm(bool en) { - u32 broadcast_bak = dramc_get_broadcast(); - dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); @@ -254,7 +341,6 @@
dramc_phy_dcm_2_channel(chn, en); } - dramc_set_broadcast(broadcast_bak); }
static void dramc_reset_delay_chain_before_calibration(void) @@ -290,7 +376,7 @@ clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); }
-void dramc_apply_config_before_calibration(void) +void dramc_apply_config_before_calibration(u8 freq_group) { dramc_enable_phy_dcm(false); dramc_reset_delay_chain_before_calibration(); @@ -331,7 +417,10 @@ clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); - clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + else + setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
dramc_rx_input_delay_tracking_init_by_freq(chn); } @@ -346,8 +435,9 @@
static void dramc_set_mr13_vrcg_to_Normal(u8 chn) { + MR13Value &= ~(0x1 << 3); for (u8 rank = 0; rank < RANK_MAX; rank++) - dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0); + dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); @@ -356,7 +446,7 @@ void dramc_apply_config_after_calibration(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); + write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7); clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2); clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); @@ -370,7 +460,8 @@ setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5);
clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24); - clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x7); + clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4); + clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf);
clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); @@ -405,12 +496,33 @@ rank << TEST2_4_TESTAGENTRK_SHIFT); }
-static void dramc_engine2_init(u8 chn, u8 rank, u32 size, bool test_pat) +static void dramc_engine2_setpat(u8 chn, bool test_pat) { - const u32 pat0 = 0x55; - const u32 pat1 = 0xaa; - const u32 addr = 0; + clrbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | + (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | + (0x1 << TEST2_4_TESTAUDBITINV_SHIFT));
+ if (!test_pat) { + setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | + (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT), + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); + } else { + clrsetbits_le32(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, + (0x11 << 8) | (0xd << 0) | (0x1 << 14)); + } + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, + (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); +} + +static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat) +{ dramc_set_rank_engine2(chn, rank);
clrbits_le32(&ch[chn].ao.dummy_rd, @@ -420,55 +532,50 @@ (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); - clrbits_le32(&ch[chn].nao.testchip_dma1, - 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT); + clrbits_le32(&ch[chn].nao.testchip_dma1, 0x1 << 12); clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); clrsetbits_le32(&ch[chn].ao.test2_0, TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, - (pat0 << TEST2_0_PAT0_SHIFT) | - (pat1 << TEST2_0_PAT1_SHIFT)); - write32(&ch[chn].ao.test2_1, (addr << 4) & 0x00ffffff); - write32(&ch[chn].ao.test2_2, (size << 4) & 0x00ffffff); + ((t2_1 >> 24) << TEST2_0_PAT0_SHIFT) | + ((t2_2 >> 24) << TEST2_0_PAT1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.test2_1, 0xfffffff0, (t2_1 & 0x00ffffff) << 4); + clrsetbits_le32(&ch[chn].ao.test2_2, 0xfffffff0, (t2_2 & 0x00ffffff) << 4);
- clrsetbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT), - ((!test_pat ? 1 : 0) << TEST2_4_TESTXTALKPAT_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDMODE_SHIFT) | - ((test_pat ? 1 : 0) << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT)); - setbits_le32(&ch[chn].ao.perfctl0, - 0x1 << PERFCTL0_RWOFOEN_SHIFT); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << TEST2_4_TESTAUDINIT_SHIFT) | - (0xd << TEST2_4_TESTAUDINC_SHIFT)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - TEST2_3_TESTCNT_MASK | (0x1 << TEST2_3_TESTAUDPAT_SHIFT), - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); + dramc_engine2_setpat(chn, test_pat); }
-static void dramc_engine2_check_complete(u8 chn) +static void dramc_engine2_check_complete(u8 chn, u8 status) { + u32 loop = 0; /* In some case test engine finished but the complete signal late come, * system will wait very long time. Hence, we set a timeout here. * After system receive complete signal or wait until time out * it will return, the caller will check compare result to verify * whether engine success. */ - if (!wait_us(10000, read32(&ch[chn].nao.testrpt) & 0x1)) - dramc_dbg("MEASURE_A timeout\n"); + while (wait_us(100, read32(&ch[chn].nao.testrpt) & status) != status) { + if (loop++ > 100) + dramc_dbg("MEASURE_A timeout\n"); + } +} + +static void dramc_engine2_compare(u8 chn, enum dram_te_op wr) +{ + u8 rank_status = ((read32(&ch[chn].ao.test2_3) & 0xf) == 1) ? 3 : 1; + + if (wr == TE_OP_WRITE_READ_CHECK) { + dramc_engine2_check_complete(chn, rank_status); + + clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); + udelay(1); + setbits_le32(&ch[chn].ao.test2_3, 0x1 << TEST2_3_TEST2W_SHIFT); + } + + dramc_engine2_check_complete(chn, rank_status); }
static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) @@ -478,26 +585,17 @@ if (wr == TE_OP_READ_CHECK) { clrbits_le32(&ch[chn].ao.test2_4, 0x1 << TEST2_4_TESTAUDMODE_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2R_SHIFT); } else if (wr == TE_OP_WRITE_READ_CHECK) { clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT), - 0x1 << TEST2_3_TEST2W_SHIFT); - - dramc_engine2_check_complete(chn); - clrbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | - (0x1 << TEST2_3_TEST2R_SHIFT) | - (0x1 << TEST2_3_TEST1_SHIFT)); - udelay(1); + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2W_SHIFT); }
- /* Do read test */ - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT), - 0x1 << TEST2_3_TEST2R_SHIFT); - - dramc_engine2_check_complete(chn); + dramc_engine2_compare(chn, wr);
udelay(1); result = read32(&ch[chn].nao.cmp_err); @@ -514,55 +612,84 @@ clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); }
-static void dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, - u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin, - u8 *pass_count, u8 *dly_fine_xt, u32 *coarse_tune, u8 *dqs_high) +static bool dramc_find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, + u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin, u8 *pass_count, + u8 *pass_count_1, u8 *dly_fine_xt, u8 *dqs_high, u8 *dqs_done) { - u16 debug_cnt_perbyte; - u8 pass_count_1[DQS_NUMBER]; + bool find_tune = false; + u16 debug_cnt_perbyte, current_pass = 0, pass_byte_cnt = 0;
for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff); u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff);
- debug_cnt_perbyte = (u16) debug_cnt[dqs]; - if (dqs_result_r != 0 || dqs_result_f != 0 || - debug_cnt_perbyte != GATING_GOLDEND_DQSCNT) + if (pass_byte_cnt & (1 << dqs)) continue; + current_pass = 0;
- if (pass_begin[dqs] == 0) { - pass_begin[dqs] = 1; - pass_count_1[dqs] = 0; - dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n", - dqs, dly_coarse_large, - dly_coarse_0p5t, *dly_fine_xt); - } + debug_cnt_perbyte = (u16) debug_cnt[dqs]; + if (dqs_result_r == 0 && dqs_result_f == 0 && + debug_cnt_perbyte == GATING_GOLDEND_DQSCNT) + current_pass = 1;
- if (pass_begin[dqs] == 1) - pass_count_1[dqs]++; + if (current_pass) { + if (pass_begin[dqs] == 0) { + pass_begin[dqs] = 1; + pass_count_1[dqs] = 0; + dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n", + dqs, dly_coarse_large, dly_coarse_0p5t, *dly_fine_xt); + }
- if (pass_begin[dqs] == 1 && - pass_count_1[dqs] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) - dqs_high[dqs] = 0; + if (pass_begin[dqs] == 1) + pass_count_1[dqs]++;
- if (pass_count_1[0] * DQS_GW_FINE_STEP > DQS_GW_FINE_END && - pass_count_1[1] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { - dramc_dbg("All bytes gating window > 1 coarse_tune," - " Early break\n"); - *dly_fine_xt = DQS_GW_FINE_END; - *coarse_tune = GATING_END; + if (pass_begin[dqs] == 1 && + pass_count_1[dqs] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { + dqs_high[dqs] = 0; + dqs_done[dqs] = 1; + } + + if (pass_count_1[0] * DQS_GW_FINE_STEP > DQS_GW_FINE_END && + pass_count_1[1] * DQS_GW_FINE_STEP > DQS_GW_FINE_END) { + dramc_dbg("All bytes gating window > 1 coarse_tune, Early break\n"); + *dly_fine_xt = DQS_GW_FINE_END; + find_tune = true; + } + } else { + if (pass_begin[dqs] != 1) + continue; + + dramc_dbg("[Byte %d] pass_begin[dqs]:%d, pass_count[dqs]:%d,pass_count_1:%d\n", + dqs, pass_begin[dqs], pass_count[dqs], pass_count_1[dqs]); + + pass_begin[dqs] = 0; + if (pass_count_1[dqs] > pass_count[dqs]) { + pass_count[dqs] = pass_count_1[dqs]; + if (pass_count_1[dqs] * DQS_GW_FINE_STEP > 32 && + pass_count_1[dqs] * DQS_GW_FINE_STEP < 96) + pass_byte_cnt |= (1 << dqs); + if (pass_byte_cnt == 3) { + *dly_fine_xt = DQS_GW_FINE_END; + find_tune = true; + } + } } } + + return find_tune; }
static void dramc_find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 dly_fine_xt, u8 *dqs_high, u8 *dly_coarse_large_cnt, - u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans) + u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans, u8 *dqs_done) { for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { u32 dqs_cnt = read32(&ch[chn].phy_nao.misc_phy_stben_b[dqs]); dqs_cnt = (dqs_cnt >> 16) & 3;
+ if (dqs_done[dqs] == 1) + continue; + if (dqs_cnt == 3) dqs_high[dqs]++;
@@ -578,9 +705,16 @@ break; case 2: case 1: + if (dqs_trans[dqs] == 1) + dramc_dbg("[Byte %ld] Lead/lag falling Transition" + " (%d, %d, %d)\n", + dqs, dly_coarse_large_cnt[dqs], + dly_coarse_0p5t_cnt[dqs], dly_fine_tune_cnt[dqs]); dqs_trans[dqs]++; break; case 0: + dramc_dbg("[Byte %ld] Lead/lag Transition tap number (%d)\n", + dqs, dqs_trans[dqs]); dqs_high[dqs] = 0; break; } @@ -610,20 +744,23 @@ burst = 1; }
- clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); - for (size_t b = 0; b < 2; b++) { clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); - clrbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); - setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); } + + clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); + setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); + + clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + udelay(1); + setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); }
static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) { - dramc_rx_dqs_isi_pulse_cg_switch(chn, false); clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT);
dramc_hw_gating_onoff(chn, false); @@ -645,8 +782,7 @@
static void dramc_write_dqs_gating_result(u8 chn, u8 rank, u8 *best_coarse_tune2t, u8 *best_coarse_tune0p5t, - u8 *best_coarse_tune2t_p1, u8 *best_coarse_tune0p5t_p1, - u8 *best_fine_tune) + u8 *best_coarse_tune2t_p1, u8 *best_coarse_tune0p5t_p1) { u8 best_coarse_rodt[DQS_NUMBER], best_coarse_0p5t_rodt[DQS_NUMBER]; u8 best_coarse_rodt_p1[DQS_NUMBER]; @@ -654,24 +790,14 @@
dramc_rx_dqs_isi_pulse_cg_switch(chn, true);
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - ((u32) best_coarse_tune2t[0] << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | - ((u32) best_coarse_tune2t[1] << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | - ((u32) best_coarse_tune2t_p1[0] << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | - ((u32) best_coarse_tune2t_p1[1] << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - ((u32) best_coarse_tune0p5t[0] << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | - ((u32) best_coarse_tune0p5t[1] << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | - ((u32) best_coarse_tune0p5t_p1[0] << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | - ((u32) best_coarse_tune0p5t_p1[1] << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) | + (best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) | + (best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12));
for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { u8 tmp_value = (best_coarse_tune2t[dqs] << 3) @@ -703,45 +829,31 @@ } }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - ((u32) best_coarse_rodt[0] << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | - ((u32) best_coarse_rodt[1] << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | - ((u32) best_coarse_rodt_p1[0] << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | - ((u32) best_coarse_rodt_p1[1] << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - ((u32) best_coarse_0p5t_rodt[0] << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | - ((u32) best_coarse_0p5t_rodt[1] << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | - ((u32) best_coarse_0p5t_rodt_p1[0] << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | - ((u32) best_coarse_0p5t_rodt_p1[1] << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); - - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - best_fine_tune[0] | (best_fine_tune[1] << 8)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) | + (best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) | + (best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12)); }
-static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) +static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group, + const struct sdram_params *params) { - u8 dqs; - const u8 mr1_value = 0x56; - u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}; + u8 dqs, fsp, freqDiv = 4; + u8 pass_begin[DQS_NUMBER] = {0}, pass_count[DQS_NUMBER] = {0}, + pass_count_1[DQS_NUMBER] = {0}, dqs_done[DQS_NUMBER] = {0}; u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], min_fine_tune[DQS_NUMBER]; u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER], best_coarse_tune2t[DQS_NUMBER]; - u8 best_coarse_tune0p5t_p1[DQS_NUMBER], - best_coarse_tune2t_p1[DQS_NUMBER]; + u8 best_coarse_tune0p5t_p1[DQS_NUMBER], best_coarse_tune2t_p1[DQS_NUMBER]; u8 dqs_high[DQS_NUMBER] = {0}, dqs_transition[DQS_NUMBER] = {0}; - u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, - dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, + u8 dly_coarse_large_cnt[DQS_NUMBER] = {0}, dly_coarse_0p5t_cnt[DQS_NUMBER] = {0}, dly_fine_tune_cnt[DQS_NUMBER] = {0}; - u32 coarse_start = GATING_START, coarse_end = GATING_END; + u32 coarse_start, coarse_end; u32 debug_cnt[DQS_NUMBER];
struct reg_value regs_bak[] = { @@ -756,23 +868,44 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr);
- dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value | 0x80); + fsp = get_freq_fsq(freq_group); + dramc_rx_dqs_isi_pulse_cg_switch(chn, false); + + MR01Value[fsp] |= 0x80; + dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]); dramc_rx_dqs_gating_cal_pre(chn, rank);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x23, true); + dramc_engine2_init(chn, rank, TEST2_1_CAL, 0xaa000023, true); + + switch (freq_group) { + case LP4X_DDR1600: + coarse_start = 18; + break; + case LP4X_DDR2400: + coarse_start = 25; + break; + case LP4X_DDR3200: + coarse_start = 25; + break; + case LP4X_DDR3600: + coarse_start = 21; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + coarse_end = coarse_start + 12;
dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; - coarse_tune += DQS_GW_COARSE_STEP) { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; - u32 dly_coarse_large_p1 = - (coarse_tune + DQS_GW_FREQ_DIV) / RX_DQS_CTL_LOOP; - u32 dly_coarse_0p5t_p1 = - (coarse_tune + DQS_GW_FREQ_DIV) % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t;
if (value >= 11) { @@ -787,49 +920,33 @@ value - (dly_coarse_large_rodt_p1 << 3); }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_large << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_large_p1 << - SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | - ((u32) dly_coarse_0p5t << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | - (dly_coarse_0p5t_p1 << - SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | - (dly_coarse_large_rodt << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_large_rodt_p1 << - SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); - write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | - (dly_coarse_0p5t_rodt_p1 << - SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (dly_coarse_large << 0) | (dly_coarse_large << 8) | + (dly_coarse_large << 16) | (dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | + (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28));
- for (u8 dly_fine_xt = DQS_GW_FINE_START; - dly_fine_xt < DQS_GW_FINE_END; - dly_fine_xt += DQS_GW_FINE_STEP) { - + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, dly_fine_xt | (dly_fine_xt << 8));
@@ -856,7 +973,7 @@ dramc_find_dly_tune(chn, dly_coarse_large, dly_coarse_0p5t, dly_fine_xt, dqs_high, dly_coarse_large_cnt, dly_coarse_0p5t_cnt, - dly_fine_tune_cnt, dqs_transition); + dly_fine_tune_cnt, dqs_transition, dqs_done);
dramc_dbg("%d %d %d |", dly_coarse_large, dly_coarse_0p5t, dly_fine_xt); @@ -871,10 +988,10 @@ }
dramc_dbg("\n"); - dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, - pass_count, &dly_fine_xt, &coarse_tune, - dqs_high); + if (dramc_find_gating_window(result_r, result_f, debug_cnt, + dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, + pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + coarse_tune = coarse_end; } }
@@ -897,7 +1014,8 @@
tmp_offset = tmp_value / RX_DQS_CTL_LOOP; best_coarse_tune2t[dqs] = min_coarse_tune2t[dqs] + tmp_offset; - tmp_value = best_coarse_tune0p5t[dqs] + DQS_GW_FREQ_DIV; + + tmp_value = best_coarse_tune0p5t[dqs] + freqDiv; best_coarse_tune0p5t_p1[dqs] = tmp_value % RX_DQS_CTL_LOOP;
tmp_offset = tmp_value / RX_DQS_CTL_LOOP; @@ -911,38 +1029,40 @@ best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);
for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d coarse dly(2T, 0.5T, fine tune)" + dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value);
- dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value & 0x7f); + MR01Value[fsp] &= 0x7f; + dramc_mode_reg_write_by_rank(chn, rank, 0x1, MR01Value[fsp]);
dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t, - best_coarse_tune0p5t, best_coarse_tune2t_p1, - best_coarse_tune0p5t_p1, best_fine_tune); + best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1); + + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + best_fine_tune[0] | (best_fine_tune[1] << 8));
dram_phy_reset(chn); }
-static void dramc_rd_dqc_init(u8 chn, u8 rank) +static void dramc_rx_rd_dqc_init(u8 chn, u8 rank) { const u8 *lpddr_phy_mapping = phy_mapping[chn]; u16 temp_value = 0;
for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT); + clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT);
- for (size_t i = 0; i < 16; i++) - temp_value |= ((0x5555 >> i) & 0x1) << lpddr_phy_mapping[i]; + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) + temp_value |= ((0x5555 >> bit) & 0x1) << lpddr_phy_mapping[bit];
u16 mr15_golden_value = temp_value & 0xff; u16 mr20_golden_value = (temp_value >> 8) & 0xff; @@ -951,14 +1071,16 @@ (mr15_golden_value << 8) | mr20_golden_value); }
-static u32 dramc_rd_dqc_run(u8 chn) +static u32 dramc_rx_rd_dqc_run(u8 chn) { + u32 loop = 0; setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT);
- if (!wait_us(100, read32(&ch[chn].nao.spcmdresp) & - (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT))) - dramc_dbg("[RDDQC] resp fail (time out)\n"); + while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 7))) { + if (loop++ > 10) + dramc_dbg("[RDDQC] resp fail (time out)\n"); + }
u32 result = read32(&ch[chn].nao.rdqc_cmp); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); @@ -967,25 +1089,22 @@ return result; }
-static void dramc_rd_dqc_end(u8 chn) +static void dramc_rx_rd_dqc_end(u8 chn) { clrbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK); }
-static void dramc_rx_vref_enable(u8 chn) +static void dramc_rx_vref_pre_setting(u8 chn) { - setbits_le32(&ch[chn].phy.b[0].dq[5], - 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT); - setbits_le32(&ch[chn].phy.b[1].dq[5], - 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT); + setbits_le32(&ch[chn].phy.b[0].dq[5], 0x1 << 16); + setbits_le32(&ch[chn].phy.b[1].dq[5], 0x1 << 16); }
-static void dramc_set_rx_vref(u8 chn, u8 value) +static void dramc_set_rx_vref(u8 chn, u8 vref) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK, - value << SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT); + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], 0x3f, vref << 0); + dramc_dbg("set rx vref :%d\n", vref); }
static void dramc_set_tx_vref(u8 chn, u8 rank, u8 value) @@ -1001,20 +1120,32 @@ dramc_set_tx_vref(chn, rank, vref); }
-static void dramc_transfer_dly_tune( - u8 chn, u32 dly, struct tx_dly_tune *dly_tune) +static void dramc_transfer_dly_tune(u8 chn, u32 dly, u32 adjust_center, + struct tx_dly_tune *dly_tune) { - u16 tmp_val; + u8 tune = 3, fine_tune = 0; + u16 tmp;
- dly_tune->fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1); + fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1); + tmp = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1;
- tmp_val = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; - dly_tune->coarse_tune_small = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large = tmp_val >> 3; + if (adjust_center) { + if (fine_tune < 10) { + fine_tune += TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP >> 1; + tmp--; + } else if (fine_tune > TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 10) { + fine_tune -= TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP >> 1; + tmp++; + } + }
- tmp_val -= 4; - dly_tune->coarse_tune_small_oen = tmp_val - ((tmp_val >> 3) << 3); - dly_tune->coarse_tune_large_oen = tmp_val >> 3; + dly_tune->fine_tune = fine_tune; + dly_tune->coarse_tune_small = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large = tmp >> tune; + + tmp -= 3; + dly_tune->coarse_tune_small_oen = tmp - ((tmp >> tune) << tune); + dly_tune->coarse_tune_large_oen = tmp >> tune; }
static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) @@ -1024,9 +1155,9 @@ switch (type) { case RX_DQ: tmp = (val << 24 | val << 16 | val << 8 | val); - for (size_t i = 2; i < 6; i++) { - write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[i], tmp); - write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[i], tmp); + for (size_t dq = 2; dq < 6; dq++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[dq], tmp); + write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[dq], tmp); } break;
@@ -1049,79 +1180,105 @@ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], mask, tmp); break; + default: + dramc_show("error calibration type:%d\n", type); + break; } }
-static void dramc_set_tx_dly_factor(u8 chn, u8 rank, - enum CAL_TYPE type, u32 val) +static void dramc_set_tx_dly_factor(u8 chn, u8 rk, + enum CAL_TYPE type, u8 *dq_small_reg, u32 dly) { struct tx_dly_tune dly_tune = {0}; - u32 coarse_tune_large = 0, coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0, coarse_tune_small_oen = 0; + u32 dly_large = 0, dly_large_oen = 0, dly_small = 0, dly_small_oen = 0; + u32 adjust_center = 0;
- dramc_transfer_dly_tune(chn, val, &dly_tune); + dramc_transfer_dly_tune(chn, dly, adjust_center, &dly_tune);
for (u8 i = 0; i < 4; i++) { - coarse_tune_large += dly_tune.coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dly_tune.coarse_tune_large_oen << (i * 4); - coarse_tune_small += dly_tune.coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dly_tune.coarse_tune_small_oen << (i * 4); + dly_large += dly_tune.coarse_tune_large << (i * 4); + dly_large_oen += dly_tune.coarse_tune_large_oen << (i * 4); + dly_small += dly_tune.coarse_tune_small << (i * 4); + dly_small_oen += dly_tune.coarse_tune_small_oen << (i * 4); } + if (type == TX_WIN_DQ_DQM) dramc_dbg("%3d |%d %d %2d | [0]", - val, dly_tune.coarse_tune_large, - dly_tune.coarse_tune_small, dly_tune.fine_tune); + dly, dly_tune.coarse_tune_large, + dly_tune.coarse_tune_small, dly_tune.fine_tune);
- if (type != TX_WIN_DQ_DQM && type != TX_WIN_DQ_ONLY) - return; + if (*dq_small_reg != dly_tune.coarse_tune_small) { + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], + 0x77777777, dly_small | (dly_small_oen << 16)); + }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + if (type == TX_WIN_DQ_DQM) { + /* Large coarse_tune setting */ + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], + 0x77777777, dly_large | (dly_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], + 0x77777777, dly_small | (dly_small_oen << 16)); + } + } + *dq_small_reg = dly_tune.coarse_tune_small;
- if (type == TX_WIN_DQ_DQM) { - /* Large coarse_tune setting */ - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - /* Fine_tune delay setting */ + if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], + FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + } + if (type == TX_WIN_DQ_DQM) { + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); } }
-static u32 dramc_get_smallest_dqs_dly( - u8 chn, u8 rank, const struct sdram_params *params) +static u32 dramc_get_smallest_dqs_dly(u8 chn, u8 rank, const struct sdram_params *params) { - u32 min_dly = 0xffff; + const u8 mck = 3; + u32 min_dly = 0xffff, virtual_delay = 0; + u32 tx_dly = read32(&ch[chn].ao.shu[0].selph_dqs0); + u32 dly = read32(&ch[chn].ao.shu[0].selph_dqs1); + u32 tmp;
- for (size_t i = 0; i < DQS_NUMBER; i++) - min_dly = MIN(min_dly, params->wr_level[chn][rank][i]); + for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { + tmp = ((tx_dly >> (dqs << 2) & 0x7) << mck) + + (dly >> (dqs << 2) & 0x7); + virtual_delay = (tmp << 5) + params->wr_level[chn][rank][dqs]; + min_dly = MIN(min_dly, virtual_delay); + }
- return DQS_DELAY + min_dly + 40; + return min_dly; }
static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type, - u16 *pre_cal, s16 *begin, s16 *end, + u8 freq_group, u16 *pre_cal, s16 *begin, s16 *end, const struct sdram_params *params) { u16 pre_dq_dly; switch (type) { case RX_WIN_RD_DQC: - *begin = FIRST_DQS_DELAY; - *end = MAX_RX_DQDLY_TAPS; - break; - case RX_WIN_TEST_ENG: - *begin = FIRST_DQ_DELAY; + switch (freq_group) { + case LP4X_DDR1600: + *begin = -48; + break; + case LP4X_DDR2400: + *begin = -30; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + *begin = -26; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + *end = MAX_RX_DQDLY_TAPS; break;
@@ -1136,394 +1293,401 @@ *begin = pre_dq_dly; *end = *begin + 64; break; + default: + dramc_show("error calibration type:%d\n", type); + break; } } -static int dramc_check_dqdqs_win( - struct dqdqs_perbit_dly *p, s16 dly_pass, s16 last_step, - bool fail, bool is_dq) + +static int dramc_check_dqdqs_win(struct win_perbit_dly *perbit_dly, + s16 dly, s16 dly_end, bool fail_bit) { - s16 best_pass_win; - struct perbit_dly *dly = is_dq ? &p->dqdly : &p->dqsdly; + int pass_win = 0;
- if (!fail && dly->first == -1) - dly->first = dly_pass; + if (perbit_dly->first_pass == PASS_RANGE_NA) { + if (!fail_bit) /* compare correct: pass */ + perbit_dly->first_pass = dly; + } else if (perbit_dly->last_pass == PASS_RANGE_NA) { + if (fail_bit) /* compare error: fail */ + perbit_dly->last_pass = dly - 1; + else if (dly == dly_end) + perbit_dly->last_pass = dly;
- if (!fail && dly->last == -2 && dly_pass == last_step) - dly->last = dly_pass; - else if (fail && dly->first != -1 && dly->last == -2) - dly->last = dly_pass - 1; + if (perbit_dly->last_pass != PASS_RANGE_NA) { + pass_win = perbit_dly->last_pass - perbit_dly->first_pass; + int best_pass_win = perbit_dly->best_last - perbit_dly->best_first; + if (pass_win >= best_pass_win) { + perbit_dly->best_last = perbit_dly->last_pass; + perbit_dly->best_first = perbit_dly->first_pass; + }
- if (dly->last == -2) - return 0; - - int pass_win = dly->last - dly->first; - best_pass_win = dly->best_last - dly->best_first; - if (pass_win > best_pass_win) { - dly->best_last = dly->last; - dly->best_first = dly->first; + /* Clear to find the next pass range if it has */ + perbit_dly->first_pass = PASS_RANGE_NA; + perbit_dly->last_pass = PASS_RANGE_NA; + } } - /* Clear to find the next pass range if it has */ - dly->first = -1; - dly->last = -2;
return pass_win; }
-static void dramc_set_vref_dly(struct vref_perbit_dly *vref_dly, - u8 vref, u32 win_size_sum, struct dqdqs_perbit_dly delay[]) +static void dramc_set_vref_dly(struct vref_perbit_dly *vref_dly, struct win_perbit_dly delay[]) { - struct dqdqs_perbit_dly *perbit_dly = vref_dly->perbit_dly; + struct win_perbit_dly *perbit_dly = vref_dly->perbit_dly;
- vref_dly->max_win = win_size_sum; - vref_dly->vref = vref; - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - perbit_dly[bit].dqdly.best = delay[bit].dqdly.best; - perbit_dly[bit].dqdly.best_first = delay[bit].dqdly.best_first; - perbit_dly[bit].dqdly.best_last = delay[bit].dqdly.best_last; - perbit_dly[bit].dqsdly.best_first = - delay[bit].dqsdly.best_first; - perbit_dly[bit].dqsdly.best_last = delay[bit].dqsdly.best_last; + for (u8 bit = 0; bit < DQ_DATA_WIDTH; bit++) { + delay[bit].win_center = (delay[bit].best_first + delay[bit].best_last) >> 1; + + perbit_dly[bit].best_first = delay[bit].best_first; + perbit_dly[bit].best_last = delay[bit].best_last; + perbit_dly[bit].win_center = delay[bit].win_center; + perbit_dly[bit].best_dqdly = delay[bit].best_dqdly; } }
static bool dramk_calc_best_vref(enum CAL_TYPE type, u8 vref, - struct vref_perbit_dly *vref_dly, - struct dqdqs_perbit_dly delay[]) + struct vref_perbit_dly *vref_dly, struct win_perbit_dly delay[], + u32 *win_min_max) { - u32 win_size; - u32 win_size_sum = 0; - static u32 min_win_size_vref; + u32 win_size, min_bit = 0xff, min_winsize = 0xffff, tmp_win_sum = 0;
switch (type) { + case RX_WIN_RD_DQC: case RX_WIN_TEST_ENG: for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_size_sum += delay[bit].dqdly.best_last - - delay[bit].dqdly.best_first + 1; - win_size_sum += delay[bit].dqsdly.best_last - - delay[bit].dqsdly.best_first + 1; + win_size = delay[bit].best_last - delay[bit].best_first; + + if (win_size < min_winsize) { + min_bit = bit; + min_winsize = win_size; + } + tmp_win_sum += win_size; } + dramc_dbg("type:%d vref:%d Min Bit=%d, min_winsize=%d, win sum:%d\n", + type, vref, min_bit, min_winsize, tmp_win_sum);
- if (win_size_sum > vref_dly->max_win) - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + if (tmp_win_sum > vref_dly->max_win_sum) { + *win_min_max = min_winsize; + vref_dly->max_win_sum = tmp_win_sum;
- if (win_size_sum < (vref_dly->max_win * 95 / 100)) + /* best vref */ + vref_dly->best_vref = vref; + } + dramc_dbg("type:%d vref:%d, win_sum_total:%d, tmp_win_sum:%d)\n", + type, vref, vref_dly->max_win_sum, tmp_win_sum); + dramc_set_vref_dly(vref_dly, delay); + + if (tmp_win_sum < vref_dly->max_win_sum * 95 / 100) { + dramc_dbg("type:%d best vref found[%d], early break! (%d < %d)\n", + type, vref_dly->best_vref, tmp_win_sum, + vref_dly->max_win_sum * 95 / 100); return true; + }
break; - case TX_DQ_DQS_MOVE_DQ_ONLY: + case TX_WIN_DQ_ONLY: + case TX_WIN_DQ_DQM: for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_size = delay[bit].dqdly.best_last - - delay[bit].dqdly.best_first + 1; - vref_dly->min_win = MIN(vref_dly->min_win, win_size); - win_size_sum += win_size; - } + win_size = delay[bit].best_last - delay[bit].best_first;
- if (win_size_sum > vref_dly->max_win - && vref_dly->min_win >= min_win_size_vref) { - min_win_size_vref = vref_dly->min_win; - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + if (win_size < min_winsize) { + min_bit = bit; + min_winsize = win_size; + } + tmp_win_sum += win_size; + } + dramc_dbg("type:%d vref:%d Min Bit=%d, min_winsize=%d, win sum:%d\n", + type, vref, min_bit, min_winsize, tmp_win_sum); + + if (min_winsize > *win_min_max || + (min_winsize == *win_min_max && + tmp_win_sum > vref_dly->max_win_sum)) { + *win_min_max = min_winsize; + vref_dly->max_win_sum = tmp_win_sum; + + /* best vref */ + vref_dly->best_vref = vref; + } + dramc_dbg("type:%d vref:%d, win_sum_total:%d, tmp_win_sum:%d)\n", + type, vref, vref_dly->max_win_sum, tmp_win_sum); + dramc_set_vref_dly(vref_dly, delay); + + if (tmp_win_sum < vref_dly->max_win_sum * 95 / 100) { + dramc_dbg("type:%d best vref found[%d], early break! (%d < %d)\n", + type, vref_dly->best_vref, tmp_win_sum, + vref_dly->max_win_sum * 95 / 100); + return true; }
break; + default: - dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + dramc_show("error calibration type:%d\n", type); break; }
return false; }
-static void dramc_calc_tx_perbyte_dly( - struct dqdqs_perbit_dly *p, s16 *win, - struct per_byte_dly *byte_delay_prop) -{ - s16 win_center = (p->dqdly.best_first + p->dqdly.best_last) >> 1; - *win = win_center; - - if (win_center < byte_delay_prop->min_center) - byte_delay_prop->min_center = win_center; - if (win_center > byte_delay_prop->max_center) - byte_delay_prop->max_center = win_center; -} - -static void dramc_set_rx_dly(u8 chn, u8 rank, s32 dly) +static void dramc_set_rx_dqdqs_dly(u8 chn, u8 rank, s32 dly) { if (dly <= 0) { - /* Hold time calibration */ + /* Set DQS delay */ dramc_set_rx_dly_factor(chn, rank, RX_DQS, -dly); dram_phy_reset(chn); } else { /* Setup time calibration */ - dramc_set_rx_dly_factor(chn, rank, RX_DQS, 0); dramc_set_rx_dly_factor(chn, rank, RX_DQM, dly); dram_phy_reset(chn); dramc_set_rx_dly_factor(chn, rank, RX_DQ, dly); } }
-static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, - struct per_byte_dly *tx_perbyte_dly, u16 dq_precal_result[]) +static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, + struct per_byte_dly *tx_perbyte_dly, u16 *dq_precal_dly, + u8 use_delay_cell, u32 *byte_dly_cell) { - u32 coarse_tune_large = 0; - u32 coarse_tune_large_oen = 0; - u32 coarse_tune_small = 0; - u32 coarse_tune_small_oen = 0; + u32 dq_large = 0, dq_large_oen = 0, dq_small = 0, dq_small_oen = 0, adjust_center = 1; + u32 dqm_large = 0, dqm_large_oen = 0, dqm_small = 0, dqm_small_oen = 0; u16 dq_oen[DQS_NUMBER] = {0}, dqm_oen[DQS_NUMBER] = {0}; struct tx_dly_tune dqdly_tune[DQS_NUMBER] = {0}; struct tx_dly_tune dqmdly_tune[DQS_NUMBER] = {0};
for (size_t i = 0; i < DQS_NUMBER; i++) { dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly, - &dqdly_tune[i]); - dramc_transfer_dly_tune(chn, dq_precal_result[i], - &dqmdly_tune[i]); + adjust_center, &dqdly_tune[i]); + dramc_transfer_dly_tune(chn, dq_precal_dly[i], + adjust_center, &dqmdly_tune[i]);
- coarse_tune_large += dqdly_tune[i].coarse_tune_large << (i * 4); - coarse_tune_large_oen += - dqdly_tune[i].coarse_tune_large_oen << (i * 4); - coarse_tune_small += dqdly_tune[i].coarse_tune_small << (i * 4); - coarse_tune_small_oen += - dqdly_tune[i].coarse_tune_small_oen << (i * 4); + dq_large += dqdly_tune[i].coarse_tune_large << (i * 4); + dq_large_oen += dqdly_tune[i].coarse_tune_large_oen << (i * 4); + dq_small += dqdly_tune[i].coarse_tune_small << (i * 4); + dq_small_oen += dqdly_tune[i].coarse_tune_small_oen << (i * 4); + + dqm_large += dqmdly_tune[i].coarse_tune_large << (i * 4); + dqm_large_oen += dqmdly_tune[i].coarse_tune_large_oen << (i * 4); + dqm_small += dqmdly_tune[i].coarse_tune_small << (i * 4); + dqm_small_oen += dqmdly_tune[i].coarse_tune_small_oen << (i * 4);
dq_oen[i] = (dqdly_tune[i].coarse_tune_large_oen << 3) + - (dqdly_tune[i].coarse_tune_small_oen << 5) + - dqdly_tune[i].fine_tune; + (dqdly_tune[i].coarse_tune_small_oen << 5) + dqdly_tune[i].fine_tune; dqm_oen[i] = (dqmdly_tune[i].coarse_tune_large_oen << 3) + - (dqmdly_tune[i].coarse_tune_small_oen << 5) + - dqmdly_tune[i].fine_tune; + (dqmdly_tune[i].coarse_tune_small_oen << 5) + + dqmdly_tune[i].fine_tune; }
for (size_t rank = rank_start; rank < RANK_MAX; rank++) { - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], - (coarse_tune_small_oen << 16) | coarse_tune_small); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], - (coarse_tune_large_oen << 16) | coarse_tune_large); - write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], - (coarse_tune_small_oen << 16) | coarse_tune_small); - } + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + 0x77777777, dq_large | (dq_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + 0x77777777, dq_small | (dq_small_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + 0x77777777, dqm_large | (dqm_large_oen << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + 0x77777777, dqm_small | (dqm_small_oen << 16));
- for (size_t rank = rank_start; rank < RANK_MAX; rank++) - for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + for (size_t byte = 0; byte < 2; byte++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, - (dqdly_tune[b].fine_tune << - FINE_TUNE_DQ_SHIFT) | - (dqmdly_tune[b].fine_tune << - FINE_TUNE_DQM_SHIFT)); + (dqdly_tune[byte].fine_tune << 8) | + (dqmdly_tune[byte].fine_tune << 16)); + if (use_delay_cell == 1) { + for (size_t byte = 0; byte < DQS_NUMBER; byte++) + write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], + byte_dly_cell[byte]); + } + + if (type != TX_WIN_DQ_ONLY) + continue; + + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, + (dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) | + (dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16)); + + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), + (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), + (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), + (dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16)); + } }
static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, - struct dqdqs_perbit_dly *dqdqs_perbit_dly, - u32 *max_dqsdly_byte, u32 *ave_dqm_dly) + struct win_perbit_dly *dly, s32 *dqsdly_byte, s32 *dqmdly_byte) { u32 value;
- for (size_t i = 0; i < DQS_NUMBER; i++) { - value = (max_dqsdly_byte[i] << 24) | - (max_dqsdly_byte[i] << 16) | - (ave_dqm_dly[i] << 8) | (ave_dqm_dly[i] << 0); - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[6], value); + /* set dqs delay, (dqm delay) */ + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) | + (dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); } dram_phy_reset(chn);
- for (size_t i = 0; i < DQ_DATA_WIDTH; i += 2) { - u32 byte = i / DQS_BIT_NUMBER; - u32 index = 2 + ((i % 8) * 2) / 4; - value = dqdqs_perbit_dly[i + 1].dqdly.best << 24 | - dqdqs_perbit_dly[i + 1].dqdly.best << 16 | - dqdqs_perbit_dly[i].dqdly.best << 8 | - dqdqs_perbit_dly[i].dqdly.best; - write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[index], value); - } -} + /* set dq delay */ + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit += 2) { + u8 index = bit + byte * DQS_BIT_NUMBER; + u8 dq_num = 2 + bit / 2; + value = (dly[index + 1].best_dqdly << 24) | + (dly[index + 1].best_dqdly << 16) | + (dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0);
-static bool dramc_calc_best_dly(u8 bit, - struct dqdqs_perbit_dly *p, u32 *p_max_byte) -{ - u8 fail = 0, hold, setup; - - hold = p->dqsdly.best_last - p->dqsdly.best_first + 1; - setup = p->dqdly.best_last - p->dqdly.best_first + 1; - - if (hold > setup) { - p->dqdly.best = 0; - p->dqsdly.best = (setup != 0) ? (hold - setup) / 2 : - (hold - setup) / 2 + p->dqsdly.best_first; - - if (p->dqsdly.best > *p_max_byte) - *p_max_byte = p->dqsdly.best; - - } else if (hold < setup) { - p->dqsdly.best = 0; - p->dqdly.best = (hold != 0) ? (setup - hold) / 2 : - (setup - hold) / 2 + p->dqdly.best_first; - - } else { /* Hold time == setup time */ - p->dqsdly.best = 0; - p->dqdly.best = 0; - - if (hold == 0) { - dramc_dbg("Error bit %d, setup = hold = 0\n", bit); - fail = 1; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], + 0x3f3f3f3f, value); } } - - dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", bit, setup, - hold, setup + hold, p->dqdly.best, p->dqsdly.best); - - return fail; }
-static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, s32 dly) +static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, u8 *small_value, s32 dly) { if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) - dramc_set_rx_dly(chn, rank, dly); + dramc_set_rx_dqdqs_dly(chn, rank, dly); else - dramc_set_tx_dly_factor(chn, rank, type, dly); + dramc_set_tx_dly_factor(chn, rank, type, small_value, dly); }
-static void dramc_set_tx_best_dly(u8 chn, u8 rank, - struct dqdqs_perbit_dly *tx_dly, u16 *tx_dq_precal_result, - const struct sdram_params *params) +static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, + struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group, + u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params) { - s16 dq_win_center[DQ_DATA_WIDTH]; - u16 pi_diff; + int index, clock_rate; + u8 use_delay_cell; u32 byte_dly_cell[DQS_NUMBER] = {0}; - struct per_byte_dly tx_perbyte_dly[DQS_NUMBER]; - u16 dly_cell_unit = params->delay_cell_unit; - int index, bit; - u16 dq_delay_cell[DQ_DATA_WIDTH]; + struct per_byte_dly center_dly[DQS_NUMBER]; + u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];
- for (size_t i = 0; i < DQS_NUMBER; i++) { - tx_perbyte_dly[i].min_center = 0xffff; - tx_perbyte_dly[i].max_center = 0; + switch (freq_group) { + case LP4X_DDR1600: + clock_rate = 800; + break; + case LP4X_DDR2400: + clock_rate = 1200; + break; + case LP4X_DDR3200: + clock_rate = 1600; + break; + case LP4X_DDR3600: + clock_rate = 1866; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; }
- for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - dramc_calc_tx_perbyte_dly(&tx_dly[i], - &dq_win_center[i], &tx_perbyte_dly[index]); - } + if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1) + use_delay_cell = 1; + else + use_delay_cell = 0;
- for (size_t i = 0; i < DQS_NUMBER; i++) { - tx_perbyte_dly[i].final_dly = tx_perbyte_dly[i].min_center; - tx_dq_precal_result[i] = (tx_perbyte_dly[i].max_center - + tx_perbyte_dly[i].min_center) >> 1; + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = 0xffff; + center_dly[byte].max_center = 0;
- for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { - pi_diff = dq_win_center[i * 8 + bit] - - tx_perbyte_dly[i].min_center; - dq_delay_cell[i * 8 + bit] = - ((pi_diff * 1000000) / (16 * 64)) - / dly_cell_unit; - byte_dly_cell[i] |= - (dq_delay_cell[i * 8 + bit] << (bit * 4)); + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < center_dly[byte].min_center) + center_dly[byte].min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > center_dly[byte].max_center) + center_dly[byte].max_center = vref_dly[index].win_center; } - - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], - byte_dly_cell[i]); + dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", + chn, rank, byte, center_dly[byte].min_center, + center_dly[byte].max_center); }
- dramc_set_tx_best_dly_factor(chn, rank, tx_perbyte_dly, - tx_dq_precal_result); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + if (use_delay_cell == 0) { + center_dly[byte].final_dly = (center_dly[byte].min_center + + center_dly[byte].max_center) >> 1; + tx_dq_precal_result[byte] = center_dly[byte].final_dly; + } else { + center_dly[byte].final_dly = center_dly[byte].min_center; + tx_dq_precal_result[byte] = (center_dly[byte].min_center + + center_dly[byte].max_center) >> 1; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + tune_diff = vref_dly[index].win_center - + center_dly[byte].min_center; + dq_delay_cell[index] = ((tune_diff * 100000000) / + (clock_rate / 2 * 64)) / dly_cell_unit; + byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); + } + } + } + + dramc_set_tx_best_dly_factor(chn, rank, type, center_dly, tx_dq_precal_result, + use_delay_cell, byte_dly_cell); }
-static int dramc_set_rx_best_dly(u8 chn, u8 rank, - struct dqdqs_perbit_dly *rx_dly) +static int dramc_set_rx_best_dly(u8 chn, u8 rank, struct win_perbit_dly *perbit_dly) { - s16 dly; - bool fail = false; - u8 index, max_limit; - static u32 max_dqsdly_byte[DQS_NUMBER]; - static u32 ave_dqmdly_byte[DQS_NUMBER]; + u8 bit_first, bit_last; + u16 u2TmpDQMSum; + s32 dqsdly_byte[DQS_NUMBER] = {0x0}, dqm_dly_byte[DQS_NUMBER] = {0x0};
- for (size_t i = 0; i < DQS_NUMBER; i++) { - max_dqsdly_byte[i] = 0; - ave_dqmdly_byte[i] = 0; - } + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + u2TmpDQMSum = 0;
- for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - fail |= dramc_calc_best_dly(i, &rx_dly[i], - &max_dqsdly_byte[index]); - } + bit_first = DQS_BIT_NUMBER * byte; + bit_last = DQS_BIT_NUMBER * byte + DQS_BIT_NUMBER - 1; + dqsdly_byte[byte] = 64;
- for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - index = i / DQS_BIT_NUMBER; - /* Set DQS to max for 8-bit */ - if (rx_dly[i].dqsdly.best < max_dqsdly_byte[index]) { - /* Delay DQ to compensate extra DQS delay */ - dly = max_dqsdly_byte[index] - rx_dly[i].dqsdly.best; - rx_dly[i].dqdly.best += dly; - max_limit = MAX_DQDLY_TAPS - 1; - if (rx_dly[i].dqdly.best > max_limit) - rx_dly[i].dqdly.best = max_limit; + for (u8 bit = bit_first; bit <= bit_last; bit++) { + if (perbit_dly[bit].win_center < dqsdly_byte[byte]) + dqsdly_byte[byte] = perbit_dly[bit].win_center; + } + dqsdly_byte[byte] = (dqsdly_byte[byte] > 0) ? 0 : -dqsdly_byte[byte]; + + for (u8 bit = bit_first; bit <= bit_last; bit++) { + perbit_dly[bit].best_dqdly = dqsdly_byte[byte] + + perbit_dly[bit].win_center; + u2TmpDQMSum += perbit_dly[bit].best_dqdly; }
- ave_dqmdly_byte[index] += rx_dly[i].dqdly.best; - if ((i + 1) % DQS_BIT_NUMBER == 0) - ave_dqmdly_byte[index] /= DQS_BIT_NUMBER; + dqm_dly_byte[byte] = u2TmpDQMSum / DQS_BIT_NUMBER; }
- if (fail) { - dramc_dbg("Fail on perbit_window_cal()\n"); - return -1; - } - - dramc_set_rx_best_dly_factor(chn, rank, rx_dly, max_dqsdly_byte, - ave_dqmdly_byte); + dramc_set_rx_best_dly_factor(chn, rank, perbit_dly, dqsdly_byte, dqm_dly_byte); return 0; }
-static void dramc_get_vref_prop(u8 rank, enum CAL_TYPE type, +static void dramc_get_vref_prop(u8 rank, enum CAL_TYPE type, u8 fsp, u8 *vref_scan_en, u8 *vref_begin, u8 *vref_end) { if (type == RX_WIN_TEST_ENG && rank == RANK_0) { *vref_scan_en = 1; - *vref_begin = RX_VREF_BEGIN; - *vref_end = RX_VREF_END; + if (fsp == FSP_0) + *vref_begin = 0x18; + else + *vref_begin = 0; + *vref_end = RX_VREF_END; } else if (type == TX_WIN_DQ_ONLY) { *vref_scan_en = 1; - *vref_begin = TX_VREF_BEGIN; - *vref_end = TX_VREF_END; + if (fsp == FSP_0) { + *vref_begin = 27 - 5; + *vref_end = 27 + 5; + } else { + *vref_begin = TX_VREF_BEGIN; + *vref_end = TX_VREF_END; + } } else { *vref_scan_en = 0; + *vref_begin = 0; + *vref_end = 1; } }
-static void dramc_engine2_setpat(u8 chn, bool test_pat) -{ - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | - (0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); - - if (!test_pat) { - setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); - - clrbits_le32(&ch[chn].ao.test2_4, - (0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | - (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | - (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT) | - (0x1 << TEST2_4_TESTXTALKPAT_SHIFT)); - } else { - clrsetbits_le32(&ch[chn].ao.test2_4, - TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, - (0x11 << 8) | (0xd << 0) | (0x1 << 14)); - } - clrsetbits_le32(&ch[chn].ao.test2_3, - (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, - (test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT); -} - static u32 dram_k_perbit(u8 chn, enum CAL_TYPE type) { u32 err_value;
if (type == RX_WIN_RD_DQC) { - err_value = dramc_rd_dqc_run(chn); + err_value = dramc_rx_rd_dqc_run(chn); + } else if (type == RX_WIN_TEST_ENG) { + err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); } else { dramc_engine2_setpat(chn, true); err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); @@ -1533,64 +1697,71 @@ return err_value; }
-static u8 dramc_window_perbit_cal(u8 chn, u8 rank, +static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, enum CAL_TYPE type, const struct sdram_params *params) { - u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1; - u8 dly_step = 2, vref_scan_enable = 0; - s16 dly, dly_begin = 0, dly_end = 0, last_step; - s16 dly_pass; - u32 dummy_rd_backup = 0, err_value, finish_bit; + u8 vref = 0, vref_begin = 0, vref_end = 1, vref_step = 1, vref_use = 0; + u8 vref_scan_enable = 0, small_reg_value = 0xff; + s16 dly, dly_begin = 0, dly_end = 0, dly_step = 1; + u32 dummy_rd_bak_engine2 = 0, err_value, finish_bit, win_min_max = 0; static u16 dq_precal_result[DQS_NUMBER]; - static struct vref_perbit_dly vref_dly; - struct dqdqs_perbit_dly dq_perbit_dly[DQ_DATA_WIDTH]; + struct vref_perbit_dly vref_dly; + struct win_perbit_dly win_perbit[DQ_DATA_WIDTH]; + u16 dly_cell_unit = params->delay_cell_unit;
- dramc_get_vref_prop(rank, type, + u8 fsp = get_freq_fsq(freq_group); + u8 vref_range = !fsp; + + dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); - if (vref_scan_enable && type == RX_WIN_RD_DQC) - dramc_rx_vref_enable(chn); + dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, + &dly_begin, &dly_end, params);
- dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d\n", - chn, rank, type, vref_scan_enable); + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) + dly_step = 2; + + dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d, vref range[%d:%d]\n", + chn, rank, type, vref_scan_enable, vref_begin, vref_end);
if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { - for (size_t i = 0; i < 2; i++) { - write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], 0); - clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[1], + for (size_t byte = 0; byte < 2; byte++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], 0xf); } - setbits_le32(&ch[chn].phy.misc_ctrl1, - 0x1 << MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT); - setbits_le32(&ch[chn].ao.dqsoscr, - 0x1 << DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT); - vref_step = 2; + setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); + setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7); + if (fsp == FSP_1) + vref_step = 2; }
if (type == RX_WIN_RD_DQC) { - dramc_rd_dqc_init(chn, rank); + dramc_rx_rd_dqc_init(chn, rank); } else { - dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + if (type == RX_WIN_TEST_ENG) + dramc_rx_vref_pre_setting(chn); + dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); }
- vref_dly.max_win = 0; - vref_dly.min_win = 0xffff; + vref_dly.max_win_sum = 0; for (vref = vref_begin; vref < vref_end; vref += vref_step) { - vref_dly.vref = vref; + small_reg_value = 0xff; finish_bit = 0; - for (size_t i = 0; i < DQ_DATA_WIDTH; i++) { - dq_perbit_dly[i].dqdly.first = -1; - dq_perbit_dly[i].dqdly.last = -2; - dq_perbit_dly[i].dqsdly.first = -1; - dq_perbit_dly[i].dqsdly.last = -2; - dq_perbit_dly[i].dqdly.best_first = -1; - dq_perbit_dly[i].dqdly.best_last = -2; - dq_perbit_dly[i].dqsdly.best_first = -1; - dq_perbit_dly[i].dqsdly.best_last = -2; + if (type == TX_WIN_DQ_ONLY) + vref_use = vref | (vref_range << 6); + else + vref_use = vref; + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + win_perbit[bit].best_first = PASS_RANGE_NA; + win_perbit[bit].best_last = PASS_RANGE_NA; }
if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_dly.vref); + dramc_set_vref(chn, rank, type, vref_use);
if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { dramc_set_rx_dly_factor(chn, rank, @@ -1599,83 +1770,73 @@ RX_DQ, FIRST_DQ_DELAY); }
- dramc_get_dly_range(chn, rank, type, dq_precal_result, - &dly_begin, &dly_end, params); for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, dly); + dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); + err_value = dram_k_perbit(chn, type); - finish_bit = 0; if (!vref_scan_enable) dramc_dbg("%d ", dly);
for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool flag; - bool fail = (err_value & ((u32) 1 << bit)) != 0; + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0;
- if (dly < 0) { - dly_pass = -dly; - last_step = -FIRST_DQS_DELAY; - flag = false; - } else { - dly_pass = dly; - last_step = dly_end; - flag = true; - } - - /* pass window bigger than 7, - consider as real pass window */ - if (dramc_check_dqdqs_win(&(dq_perbit_dly[bit]), - dly_pass, last_step, - fail, flag) > 7) + /* pass window bigger than 7, consider as real pass window */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) finish_bit |= (1 << bit);
if (vref_scan_enable) continue; - dramc_dbg("%s", !fail ? "o" : "x"); + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); }
if (!vref_scan_enable) dramc_dbg(" [MSB]\n"); - if (finish_bit == ((1 << DQ_DATA_WIDTH) - 1)) { - dramc_dbg("all bits window found, break!\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, early break! delay=0x%x\n", + dly); break; } }
for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win(%d ~ %d)\n", bit, - dq_perbit_dly[bit].dqdly.best_first, - dq_perbit_dly[bit].dqdly.best_last); + dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, + win_perbit[bit].best_first, win_perbit[bit].best_last, + win_perbit[bit].best_last - win_perbit[bit].best_first);
- if (dramk_calc_best_vref(type, vref, &vref_dly, dq_perbit_dly)) + if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) break; - - if (finish_bit == ((1 << DQ_DATA_WIDTH) - 1)) { - dramc_dbg("all bits window found, break!\n"); - break; - } }
if (type == RX_WIN_RD_DQC) { - dramc_rd_dqc_end(chn); + dramc_rx_rd_dqc_end(chn); } else { dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); }
- if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_dly.vref); + if (vref_scan_enable && type == RX_WIN_TEST_ENG) + dramc_set_vref(chn, rank, type, vref_dly.best_vref);
if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); else - dramc_set_tx_best_dly(chn, rank, vref_dly.perbit_dly, - dq_precal_result, params); + dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); + + if (vref_scan_enable && type == TX_WIN_DQ_ONLY) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + return 0; }
-static void dramc_dle_factor_handler(u8 chn, u8 val) +static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group) { + u8 start_ext2 = 0, start_ext3 = 0, last_ext2 = 0, last_ext3 = 0; + val = MAX(val, 2); clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], SHU_CONF1_DATLAT_MASK | SHU_CONF1_DATLAT_DSEL_MASK | @@ -1683,94 +1844,106 @@ (val << SHU_CONF1_DATLAT_SHIFT) | ((val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) | ((val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT)); + + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + start_ext2 = 1; + + if (val >= 24) + last_ext2 = last_ext3 = 1; + else if (val >= 18) + last_ext2 = 1; + + clrsetbits_le32(&ch[chn].ao.shu[0].pipe, (0x1 << 31) | (0x1 << 30) | (0x1 << 29) | + (0x1 << 28) | (0x1 << 27) | (0x1 << 26), + (0x1 << 31) | (0x1 << 30) | (start_ext2 << 29) | + (last_ext2 << 28) | (start_ext3 << 27) | (last_ext3 << 26)); dram_phy_reset(chn); }
-static u8 dramc_rx_datlat_cal(u8 chn, u8 rank) +static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { - s32 datlat, first = -1, sum = 0, best_step; + u32 datlat, begin = 0, first = 0, sum = 0, best_step; + u32 datlat_start = 7;
best_step = read32(&ch[chn].ao.shu[0].conf[1]) & SHU_CONF1_DATLAT_MASK;
- dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: %2x\n", - chn, rank, best_step); + dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n", + chn, rank, best_step);
u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, 0x400, false); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false);
- for (datlat = 12; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat); + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group);
u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - - if (err != 0 && first != -1) - break; - - if (sum >= 4) - break; - if (err == 0) { - if (first == -1) + if (begin == 0) { first = datlat; - sum++; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; }
- dramc_dbg("Datlat=%2d, err_value=0x%8x, sum=%d\n", - datlat, err, sum); + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); }
dramc_engine2_end(chn); write32(&ch[chn].ao.dummy_rd, dummy_rd_backup);
- best_step = first + (sum >> 1); - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - first, sum, best_step); - assert(sum != 0);
- dramc_dle_factor_handler(chn, best_step); + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step);
- clrsetbits_le32(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND_MASK, + dramc_dle_factor_handler(chn, best_step, freq_group); + + clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), (0x1 << PADCTRL_DQIENQKEND_SHIFT) | (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT));
return (u8) best_step; }
-static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 datlat0, u8 datlat1) +static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 freq_group, u8 datlat0, u8 datlat1) { u8 final_datlat = MAX(datlat0, datlat1); - dramc_dle_factor_handler(chn, final_datlat); + dramc_dle_factor_handler(chn, final_datlat, freq_group); }
-static void dramc_rx_dqs_gating_post_process(u8 chn) +static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) { - u8 rank_rx_dvs, dqsinctl; - u32 read_dqsinctl, rankinctl_root, xrtr2r, reg_tx_dly_dqsgated_min = 3; + s8 dqsinctl; + u32 read_dqsinctl, rankinctl_root, reg_tx_dly_dqsgated_min = 3; u8 txdly_cal_min = 0xff, txdly_cal_max = 0, tx_dly_dqs_gated = 0; u32 best_coarse_tune2t[RANK_MAX][DQS_NUMBER]; u32 best_coarse_tune2t_p1[RANK_MAX][DQS_NUMBER];
- rank_rx_dvs = reg_tx_dly_dqsgated_min - 1; + if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) + reg_tx_dly_dqsgated_min = 2; + else + reg_tx_dly_dqsgated_min = 1;
- for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], - SHU1_BX_DQ7_R_DMRANKRXDVS_MASK, - rank_rx_dvs << SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT); - + /* get TXDLY_Cal_min and TXDLY_Cal_max value */ for (size_t rank = 0; rank < RANK_MAX; rank++) { u32 dqsg0 = read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0); for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { - best_coarse_tune2t[rank][dqs] = - (dqsg0 >> (dqs * 8)) & - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK; - best_coarse_tune2t_p1[rank][dqs] = - ((dqsg0 >> (dqs * 8)) & - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK) >> - SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT; + best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7; + best_coarse_tune2t_p1[rank][dqs] = (dqsg0 >> (dqs * 8 + 4)) & 0x7; dramc_dbg("Rank%zd best DQS%zd dly(2T,(P1)2T)=(%d, %d)\n", - rank, dqs, best_coarse_tune2t[rank][dqs], - best_coarse_tune2t_p1[rank][dqs]); + rank, dqs, best_coarse_tune2t[rank][dqs], + best_coarse_tune2t_p1[rank][dqs]);
tx_dly_dqs_gated = best_coarse_tune2t[rank][dqs]; txdly_cal_min = MIN(txdly_cal_min, tx_dly_dqs_gated); @@ -1781,8 +1954,8 @@ }
dqsinctl = reg_tx_dly_dqsgated_min - txdly_cal_min; - dramc_dbg("Dqsinctl:%d, tx_dly_dqsgated_min %d, txdly_cal_min %d\n", - dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min); + dramc_dbg("Dqsinctl:%d, dqsgated_min %d, txdly_cal_min %d, txdly_cal_max %d\n", + dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min, txdly_cal_max);
if (dqsinctl != 0) { txdly_cal_min += dqsinctl; @@ -1795,13 +1968,13 @@ best_coarse_tune2t_p1[rank][dqs] += dqsinctl;
dramc_dbg("Best DQS%zd dly(2T) = (%d)\n", - dqs, best_coarse_tune2t[rank][dqs]); + dqs, best_coarse_tune2t[rank][dqs]); dramc_dbg("Best DQS%zd P1 dly(2T) = (%d)\n", - dqs, - best_coarse_tune2t_p1[rank][dqs]); + dqs, best_coarse_tune2t_p1[rank][dqs]); }
- write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, (best_coarse_tune2t[rank][0] << 0) | (best_coarse_tune2t[rank][1] << 8) | (best_coarse_tune2t_p1[rank][0] << 4) | @@ -1811,51 +1984,39 @@
read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) & SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl; - rankinctl_root = (read_dqsinctl >= 3) ? (read_dqsinctl - 3) : 0; + rankinctl_root = (read_dqsinctl >= 2) ? (read_dqsinctl - 2) : 0;
- clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, - SHURK_DQSCTL_DQSINCTL_MASK, - read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, - SHURK_DQSCTL_DQSINCTL_MASK, - read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf, read_dqsinctl << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf, read_dqsinctl << 0); clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, - SHU_RANKCTL_RANKINCTL_PHY_MASK | - SHU_RANKCTL_RANKINCTL_MASK | SHU_RANKCTL_RANKINCTL_ROOT1_MASK, - (read_dqsinctl << SHU_RANKCTL_RANKINCTL_PHY_SHIFT) | - (rankinctl_root << SHU_RANKCTL_RANKINCTL_SHIFT) | - (rankinctl_root << SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT)); + (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, + (read_dqsinctl << 28) | (rankinctl_root << 20) | + (rankinctl_root << 24) | rankinctl_root);
- xrtr2r = MIN(8 + txdly_cal_max + 1, 12); - clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, - SHU_ACTIM_XRT_XRTR2R_MASK, - xrtr2r << SHU_ACTIM_XRT_XRTR2R_SHIFT); - - dramc_dbg("Tx_dly_DQS gated check: min %d max %d, changeDQSINCTL=%d," - " DQSINCTL=%d, RANKINCTL=%d, XRTR2R=%d\n", - txdly_cal_min, txdly_cal_max, dqsinctl, - read_dqsinctl, rankinctl_root, xrtr2r); + u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1; + clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), + (0xff << 8) | (0x9 << 2) | ROEN); }
-void dramc_calibrate_all_channels(const struct sdram_params *pams) +void dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group) { u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { dramc_show("Start K ch:%d, rank:%d\n", chn, rk); dramc_auto_refresh_switch(chn, false); - dramc_cmd_bus_training(chn, rk, pams); - dramc_write_leveling(chn, rk, pams->wr_level); + dramc_cmd_bus_training(chn, rk, freq_group, pams); + dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); - dramc_rx_dqs_gating_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); - dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); - rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk); - dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); + dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_RD_DQC, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_DQM, pams); + dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_ONLY, pams); + rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk, freq_group, pams); + dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams); }
- dramc_rx_dqs_gating_post_process(chn); - dramc_dual_rank_rx_datlat_cal(chn, rx_datlat[0], rx_datlat[1]); + dramc_rx_dqs_gating_post_process(chn, freq_group); + dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } } diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 26e8260..a582fe0 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -19,6 +19,17 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h>
+#define LP4X_HIGH_FREQ LP4X_DDR3200 +#define LP4X_MIDDLE_FREQ LP4X_DDR2400 +#define LP4X_LOW_FREQ LP4X_DDR1600 + +u32 frequency_table[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = 1600, + [LP4X_DDR2400] = 2400, + [LP4X_DDR3200] = 3200, + [LP4X_DDR3600] = 3600, +}; + struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { [CHANNEL_A] = { @@ -32,6 +43,12 @@ } };
+struct optimize_ac_time { + u8 rfc; + u8 rfc_05t; + u16 tx_ref_cnt; +}; + void dramc_set_broadcast(u32 onoff) { write32(&mt8183_infracfg->dramc_wbr, onoff); @@ -268,17 +285,31 @@ setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31); }
-static void dramc_ac_timing_optimize(void) +static void dramc_ac_timing_optimize(u8 freq_group) { + struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, + [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, + }; + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, 0x64 << 16); - clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, 0x1 << 2); + 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + rf_cab_opt[freq_group].rfc_05t << 2); clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, 0x77 << 0); + 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); } }
+static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) +{ + dramc_init(params, freq_group); + dramc_apply_config_before_calibration(freq_group); +} + static void init_dram(const struct sdram_params *params, u8 freq_group) { global_option_init(params); @@ -289,7 +320,7 @@ dramc_sw_impedance_cal(params, ODT_OFF); dramc_sw_impedance_cal(params, ODT_ON);
- dramc_init(params, freq_group); + dfs_init_for_calibration(params, freq_group); emi_init2(params); }
@@ -302,17 +333,25 @@ clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); }
-static void do_calib(const struct sdram_params *params) +static void do_calib(const struct sdram_params *params, u8 freq_group) { - dramc_apply_config_before_calibration(); - dramc_calibrate_all_channels(params); - dramc_ac_timing_optimize(); + dramc_show("Start K freq group:%d\n", frequency_table[freq_group]); + dramc_calibrate_all_channels(params, freq_group); + dramc_ac_timing_optimize(freq_group); + dramc_show("%s K freq group:%d finish!\n", __func__, frequency_table[freq_group]); +} + +static void after_calib(void) +{ dramc_apply_config_after_calibration(); dramc_runtime_config(); }
void mt_set_emi(const struct sdram_params *params) { - init_dram(params, LP4X_DDR3200); - do_calib(params); + u32 current_freq = LP4X_HIGH_FREQ; + + init_dram(params, current_freq); + do_calib(params, current_freq); + after_calib(); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index a2ff08d..1ce5f67 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -50,16 +50,6 @@ };
enum { - TX_DQ_DQS_MOVE_DQ_ONLY = 0, - TX_DQ_DQS_MOVE_DQM_ONLY, - TX_DQ_DQS_MOVE_DQ_DQM -}; - -enum { - MAX_CA_FINE_TUNE_DELAY = 63, - MAX_CS_FINE_TUNE_DELAY = 63, - MAX_CLK_FINE_TUNE_DELAY = 31, - CATRAINING_NUM = 6, PASS_RANGE_NA = 0x7fff };
@@ -76,10 +66,8 @@
enum { DQS_GW_COARSE_STEP = 1, - DQS_GW_FINE_START = 0, DQS_GW_FINE_END = 32, DQS_GW_FINE_STEP = 4, - DQS_GW_FREQ_DIV = 4, RX_DQS_CTL_LOOP = 8, RX_DLY_DQSIENSTB_LOOP = 32 }; @@ -102,10 +90,6 @@ DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16,
- DQS_DELAY_2T = 3, - DQS_DELAY_0P5T = 4, - DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5, - SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), @@ -124,9 +108,10 @@ void dramc_init(const struct sdram_params *params, u8 freq_group); void dramc_sw_impedance_save_reg(u8 freq_group); void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); -void dramc_apply_config_before_calibration(void); +void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(void); -void dramc_calibrate_all_channels(const struct sdram_params *params); +void dramc_calibrate_all_channels(const struct sdram_params *pams, + u8 freq_group); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 8bed1ba..fb8d7d7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -945,15 +945,12 @@ };
enum { + MISC_STATUSA_SREF_STATE = 16, MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000, };
enum { - SPCMDRESP_RDDQC_RESPONSE_SHIFT = 7, -}; - -enum { DDRCONF0_DM4TO1MODE_SHIFT = 22, DDRCONF0_RDATRST_SHIFT = 0, }; @@ -974,6 +971,8 @@ };
enum { + MRS_MPCRK_SHIFT = 28, + MRS_MPCRK_MASK = 0x30000000, MRS_MRSRK_SHIFT = 24, MRS_MRSRK_MASK = 0x03000000, MRS_MRSMA_SHIFT = 8,
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34332 )
Change subject: mediatek/mt8183: Support more DRAM frequency bootup ......................................................................
Patch Set 44:
thanks, Patrick!
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