Change in coreboot[master]: soc/intel/common/block/fast_spi: Refactor ROM caching implementation

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63221 )

Change subject: soc/intel/common/block/fast_spi: Refactor ROM caching implementation
......................................................................

soc/intel/common/block/fast_spi: Refactor ROM caching implementation

This patch removes different implementation to cache the SPI ROM between
early and later boot stage where SPI ROM caching doesn't need even
advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage
is always mapped to below 4GB hence, simple `set_var_mtrr()` function
can be sufficient without any additional complexity.

BUG=b:225766934
TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able
to update the temporary variable range MTRRs and showed ~44ms of boot
time savings as below:

Before:
  90:starting to load payload                    1,084,052 (14)
  15:starting LZMA decompress (ignore for x86)   1,084,121 (68)
  16:finished LZMA decompress (ignore for x86)   1,140,742 (56,620)

After:
  90:starting to load payload                    1,090,433 (14)
  15:starting LZMA decompress (ignore for x86)   1,090,650 (217)
  16:finished LZMA decompress (ignore for x86)   1,102,896 (12,245)

Signed-off-by: Subrata Banik 
Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 12 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63221/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 7be71a2..be0e319 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -196,6 +196,16 @@
    write32(spibar + SPIBAR_RESET_LOCK, ssl);
 }

+static void fast_spi_enable_cache_range(unsigned int base, unsigned int size)
+{
+	const int type = MTRR_TYPE_WRPROT;
+	int mtrr = get_free_var_mtrr();
+	if (mtrr == -1)
+		return;
+
+	set_var_mtrr(mtrr, base, size, type);
+}
+
 /*
  * Returns bios_start and fills in size of the BIOS region.
  */
@@ -240,19 +250,11 @@
 {
    size_t ext_bios_size;
    uintptr_t ext_bios_base;
-	const int type = MTRR_TYPE_WRPROT;

if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size))
    	return;

-	if (ENV_PAYLOAD_LOADER) {
-		mtrr_use_temp_range(ext_bios_base, ext_bios_size, type);
-	} else {
-		int mtrr = get_free_var_mtrr();
-		if (mtrr == -1)
-			return;
-		set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type);
-	}
+	fast_spi_enable_cache_range(ext_bios_base, ext_bios_size);
 }

void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf)
@@ -271,7 +273,6 @@
 {
    size_t bios_size;
    uint32_t alignment;
-	const int type = MTRR_TYPE_WRPROT;
    uintptr_t base;

/* Only the IFD BIOS region is memory mapped (at top of 4G) */
@@ -290,16 +291,7 @@
    bios_size = ALIGN_UP(bios_size, alignment);
    base = 4ULL*GiB - bios_size;

-	if (ENV_PAYLOAD_LOADER) {
-		mtrr_use_temp_range(base, bios_size, type);
-	} else {
-		int mtrr = get_free_var_mtrr();
-
-		if (mtrr == -1)
-			return;
-
-		set_var_mtrr(mtrr, base, bios_size, type);
-	}
+	fast_spi_enable_cache_range(base, bios_size);

/* Check if caching is needed for extended bios region if supported */
    fast_spi_cache_ext_bios_window();