Change in coreboot[master]: soc/amd/sabrina: Disable lpc ldrq function

[Jon Murphy (Code Review)]

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63703 )

Change subject: soc/amd/sabrina: Disable lpc ldrq function
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soc/amd/sabrina: Disable lpc ldrq function

Add function to disable lpc ldrq for espi.

BUG=b:227282870
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Jon Murphy 
Change-Id: I680c10dc8916c23ce6934d87aee5e484d4a84b78
---
M src/soc/amd/sabrina/espi_util.c
M src/soc/amd/sabrina/include/soc/espi.h
2 files changed, 21 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63703/1

diff --git a/src/soc/amd/sabrina/espi_util.c b/src/soc/amd/sabrina/espi_util.c
index 20db1b6..bad0589 100644
--- a/src/soc/amd/sabrina/espi_util.c
+++ b/src/soc/amd/sabrina/espi_util.c
@@ -1,14 +1,23 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <amdblocks/acpimmio.h>
+#include <amdblocks/lpc.h>
+#include <device/pci_ops.h>
 #include <amdblocks/spi.h>
 #include <soc/espi.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 #include <types.h>

-#define ESPI_CNTRL_REGISTER	0x10
-#define  LOCK_SPIX10_BIT2	BIT(3)
-#define  ESPI_MUX_SPI1		BIT(2)
-#define  ROM_ADDR_WR_PROT	BIT(1)
-#define  DIS_ESPI_MASCTL_REG_WR	BIT(0)
+void espi_disable_lpc_ldrq(void)
+{
+	/* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped
+	   on Picasso and older compared to Renoir/Cezanne and newer */
+	uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
+	dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN);
+	dword |= LPC_LDRQ0_PD_EN;
+	pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
+}

void espi_switch_to_spi1_pads(void)
 {
diff --git a/src/soc/amd/sabrina/include/soc/espi.h b/src/soc/amd/sabrina/include/soc/espi.h
index 76af3a1..5631ede 100644
--- a/src/soc/amd/sabrina/include/soc/espi.h
+++ b/src/soc/amd/sabrina/include/soc/espi.h
@@ -3,6 +3,13 @@
 #ifndef AMD_SABRINA_ESPI_H
 #define AMD_SABRINA_ESPI_H

+#define ESPI_CNTRL_REGISTER	0x10
+#define  LOCK_SPIX10_BIT2	BIT(3)
+#define  ESPI_MUX_SPI1		BIT(2)
+#define  ROM_ADDR_WR_PROT	BIT(1)
+#define  DIS_ESPI_MASCTL_REG_WR	BIT(0)
+
+void espi_disable_lpc_ldrq(void);
 void espi_switch_to_spi1_pads(void);

#endif /* AMD_SABRINA_ESPI_H */