Patch merged into coreboot/master: nb/intel/gm45: Fix panel-power-sequence clock divisor

the following patch was just integrated into master:
commit d85a71a75c35b5bf683939e320ff7a501f89f583
Author: Nico Huber 
Date:   Sun Nov 27 14:43:12 2016 +0100

nb/intel/gm45: Fix panel-power-sequence clock divisor

We kept this value at it's default on the native graphics init path.
    Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.

The panel power sequencer uses the core display clock (CDCLK). It's
    based on the HPLLVCO and a frequency selection we made during raminit.
    The value written is the (actual divisor/2)-1 for a 100us timer.

v2: Fix unaligned mmio access inherited from Linux.

v3: Use MCHBAR8() instead. Also, the unaligned access might have
        worked after all.

Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
    Signed-off-by: Nico Huber 
    Reviewed-on: https://review.coreboot.org/17619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Arthur Heymans

See https://review.coreboot.org/17619 for details.

-gerrit