Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Deepti Deshatty.
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50996

to look at the new patch set (#8).

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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mb/adlrvp: Fix DDR5 Boot issue

Signed-off-by: Meera Ravindranath 
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
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M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/8