Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81464?usp=email )
Change subject: sb: Remove blank lines before '}' and after '{' ......................................................................
sb: Remove blank lines before '}' and after '{'
Change-Id: Ib7fcca7dcf7daec0254f687b2a8e9a908f28a1aa Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c 11 files changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81464/1
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index d5766d8..355e9df 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -114,5 +114,4 @@ } acpigen_pop_len(); acpigen_pop_len(); - } diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 8b19b7d..1594e68 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -320,7 +320,6 @@ host_and_or(base, SMBHSTCTL, 0xff, SMBHSTCNT_LAST_BYTE); } - }
/* Engine internally completes the transaction diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 93185d4..068062b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -913,7 +913,6 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { - if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash);
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e78ba42..3477e3a 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -16,7 +16,6 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 2333c76..31aeaf6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -54,7 +54,6 @@ config->sata_mode = SATA_MODE_IDE_PLAIN; printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n"); } - }
if (config->sata_mode == SATA_MODE_AHCI) { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a374068..e01edf2 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -52,7 +52,6 @@
/* Enable expresscard hotplug events. */ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - pci_or_config32(dev, 0xd8, 1 << 30); pci_write_config16(dev, 0x42, 0x142); } diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 3ed9d60..0068fb1 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -52,7 +52,6 @@
/* Enable expresscard hotplug events. */ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - pci_or_config32(dev, 0xd8, 1 << 30); pci_write_config16(dev, 0x42, 0x142); } diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index 4ca8010..b04b8e3 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -20,7 +20,6 @@ pci_write_config32(dev, ACNF, dword); byte = 0x08; pci_write_config8(dev, MTT, byte); - } static struct device_operations pcix_ops = { .read_resources = pci_bus_read_resources, diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 7d31b3e..7f5e1fa 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -231,7 +231,6 @@ rp = root_port_number(dev);
if (!is_rp_enabled(rp)) { - /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) pci_or_config8(dev, 0xe1, 0x3c); diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index f78f816..645e5f1 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -142,7 +142,6 @@
static void rl5c476_read_resources(struct device *dev) { - struct resource *resource;
/* For CF socket we need an extra memory window for @@ -173,7 +172,6 @@ }
pci_dev_set_resources(dev); - }
static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor, diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 55d37af..2257c26 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -10,7 +10,6 @@
static void ti_pci1x2y_init(struct device *dev) { - printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
-
Elyes Haouas (Code Review)