Change in ...coreboot[master]: mainboard: Add Clevo W650SZ - coreboot-gerrit

8 Jun 2019

Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33325
to review the following change.
Change subject: mainboard: Add Clevo W650SZ
......................................................................
mainboard: Add Clevo W650SZ
This port is based on the code generated with autoport with Haswell
support (30890).
This laptop has two flash chips with 2MB(ME)+4MB(BIOS), so it depends
on 30980.
Now it can boot Arch Linux from a USB flash disk with SeaBIOS payload.
The EHCI debug port is at the right hand side of the laptop, but the
debug message stops to display after mrc.bin initializes USB.
Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923
Signed-off-by: Iru Cai mytbk920423@gmail.com
---
A src/mainboard/clevo/Kconfig
A src/mainboard/clevo/Kconfig.name
A src/mainboard/clevo/w650sz/Kconfig
A src/mainboard/clevo/w650sz/Kconfig.name
A src/mainboard/clevo/w650sz/Makefile.inc
A src/mainboard/clevo/w650sz/acpi/ec.asl
A src/mainboard/clevo/w650sz/acpi/platform.asl
A src/mainboard/clevo/w650sz/acpi/superio.asl
A src/mainboard/clevo/w650sz/acpi_tables.c
A src/mainboard/clevo/w650sz/board_info.txt
A src/mainboard/clevo/w650sz/devicetree.cb
A src/mainboard/clevo/w650sz/dsdt.asl
A src/mainboard/clevo/w650sz/gma-mainboard.ads
A src/mainboard/clevo/w650sz/gpio.c
A src/mainboard/clevo/w650sz/hda_verb.c
A src/mainboard/clevo/w650sz/mainboard.c
A src/mainboard/clevo/w650sz/romstage.c
17 files changed, 728 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33325/1

diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig
new file mode 100644
index 0000000..9aacf38
--- /dev/null
+++ b/src/mainboard/clevo/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_CLEVO
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/clevo/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/clevo/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Clevo"
+
+endif
diff --git a/src/mainboard/clevo/Kconfig.name b/src/mainboard/clevo/Kconfig.name
new file mode 100644
index 0000000..2e72ffa
--- /dev/null
+++ b/src/mainboard/clevo/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_NOTEBOOK
+	bool "Clevo"
diff --git a/src/mainboard/clevo/w650sz/Kconfig b/src/mainboard/clevo/w650sz/Kconfig
new file mode 100644
index 0000000..61b740c
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_NOTEBOOK_W650SZ
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_6144
+	select CPU_INTEL_HASWELL
+	select EC_ACPI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SYSTEM_TYPE_LAPTOP
+	select TSC_MONOTONIC_TIMER
+
+config MAINBOARD_DIR
+	string
+	default notebook/w650sz
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "W650SZ"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0416.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,0416"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x655
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1558
+
+config MAX_CPUS
+	int
+	default 8
+
+config USBDEBUG_HCD_INDEX
+	int
+	default 2
+
+endif
diff --git a/src/mainboard/clevo/w650sz/Kconfig.name b/src/mainboard/clevo/w650sz/Kconfig.name
new file mode 100644
index 0000000..f2ec7e4
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_NOTEBOOK_W650SZ
+	bool "W650SZ"
diff --git a/src/mainboard/clevo/w650sz/Makefile.inc b/src/mainboard/clevo/w650sz/Makefile.inc
new file mode 100644
index 0000000..ebe01ae
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/clevo/w650sz/acpi/ec.asl b/src/mainboard/clevo/w650sz/acpi/ec.asl
new file mode 100644
index 0000000..f2f4269
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/acpi/ec.asl
@@ -0,0 +1,7 @@
+Device(EC)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 0)
+	Name (_GPE, 23)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/clevo/w650sz/acpi/platform.asl b/src/mainboard/clevo/w650sz/acpi/platform.asl
new file mode 100644
index 0000000..c2862c9
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/acpi/platform.asl
@@ -0,0 +1,10 @@
+Method(_WAK,1)
+{
+        /* FIXME: EC support  */
+	Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+        /* FIXME: EC support  */
+}
diff --git a/src/mainboard/clevo/w650sz/acpi/superio.asl b/src/mainboard/clevo/w650sz/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/clevo/w650sz/acpi_tables.c b/src/mainboard/clevo/w650sz/acpi_tables.c
new file mode 100644
index 0000000..5dc98d8
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function.  */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	// the lid is open by default.
+	gnvs->lids = 1;
+
+	gnvs->tcrt = 100;
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/clevo/w650sz/board_info.txt b/src/mainboard/clevo/w650sz/board_info.txt
new file mode 100644
index 0000000..cdbf8b8
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/board_info.txt
@@ -0,0 +1,4 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/clevo/w650sz/devicetree.cb b/src/mainboard/clevo/w650sz/devicetree.cb
new file mode 100644
index 0000000..223253e
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/devicetree.cb
@@ -0,0 +1,116 @@
+chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+	register "gfx.ndid" = "3"
+	register "gpu_cpu_backlight" = "0x041e041e"
+	register "gpu_ddi_e_connected" = "1"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_port_select" = "0"
+	register "gpu_panel_power_backlight_off_delay" = "1"
+	register "gpu_panel_power_backlight_on_delay" = "1"
+	register "gpu_panel_power_cycle_delay" = "6"
+	register "gpu_panel_power_down_delay" = "500"
+	register "gpu_panel_power_up_delay" = "2000"
+	register "gpu_pch_backlight" = "0x041e041e"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/haswell
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on
+			end
+			device lapic 0xacac off
+			end
+		end
+	end
+	device domain 0x0 on
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "gen1_dec" = "0x000c0069"
+			register "gen2_dec" = "0x000c3321"
+			register "gen3_dec" = "0x00000000"
+			register "gen4_dec" = "0x00000000"
+			register "gpi7_routing" = "2"
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x80"
+			register "pirqc_routing" = "0x83"
+			register "pirqd_routing" = "0x8a"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x85"
+			register "pirqh_routing" = "0x84"
+			register "sata_ahci" = "1"
+			register "sata_port_map" = "0x25"
+			device pci 14.0 on # xHCI Controller
+				subsystemid 0x1558 0x0655
+			end
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x1558 0x0655
+			end
+			device pci 16.1 off # Management Engine Interface 2
+			end
+			device pci 16.2 off # Management Engine IDE-R
+			end
+			device pci 16.3 off # Management Engine KT
+			end
+			device pci 19.0 off # Intel Gigabit Ethernet
+			end
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1b.0 on # High Definition Audio Audio controller
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1c.1 off # PCIe Port #2
+			end
+			device pci 1c.2 on # PCIe Port #3
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1c.3 on # PCIe Port #4
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1c.4 off # PCIe Port #5
+			end
+			device pci 1c.5 off # PCIe Port #6
+			end
+			device pci 1c.6 off # PCIe Port #7
+			end
+			device pci 1c.7 off # PCIe Port #8
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x1558 0x0655
+			end
+			device pci 1f.5 off # SATA Controller 2
+			end
+			device pci 1f.6 off # Thermal
+			end
+		end
+		device pci 00.0 on # Host bridge Host bridge
+			subsystemid 0x1558 0x0655
+		end
+		device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01
+			subsystemid 0x1558 0x0655
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x1558 0x0655
+		end
+		device pci 03.0 on # Mini-HD audio Audio controller
+			subsystemid 0x1558 0x0655
+		end
+	end
+end
diff --git a/src/mainboard/clevo/w650sz/dsdt.asl b/src/mainboard/clevo/w650sz/dsdt.asl
new file mode 100644
index 0000000..f3ed3d2
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/dsdt.asl
@@ -0,0 +1,29 @@
+#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI 2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	// OEM revision
+)
+{
+	/* Some generic macros */
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/lynxpoint/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+
+	Device (_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/clevo/w650sz/gma-mainboard.ads b/src/mainboard/clevo/w650sz/gma-mainboard.ads
new file mode 100644
index 0000000..ce27742
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/gma-mainboard.ads
@@ -0,0 +1,35 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   -- FIXME: check this
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      Internal,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/clevo/w650sz/gpio.c b/src/mainboard/clevo/w650sz/gpio.c
new file mode 100644
index 0000000..5bcc83e
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/gpio.c
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_OUTPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio2 = GPIO_LEVEL_LOW,
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio11 = GPIO_LEVEL_HIGH,
+	.gpio13 = GPIO_LEVEL_HIGH,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio19 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio8 = GPIO_RESET_RSMRST,
+	.gpio24 = GPIO_RESET_RSMRST,
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio3 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_GPIO,
+	.gpio41 = GPIO_MODE_GPIO,
+	.gpio42 = GPIO_MODE_GPIO,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_GPIO,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_OUTPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_OUTPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_HIGH,
+	.gpio36 = GPIO_LEVEL_HIGH,
+	.gpio37 = GPIO_LEVEL_HIGH,
+	.gpio38 = GPIO_LEVEL_HIGH,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_HIGH,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio52 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio54 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio46 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_OUTPUT,
+	.gpio65 = GPIO_DIR_OUTPUT,
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio67 = GPIO_DIR_OUTPUT,
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_OUTPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_HIGH,
+	.gpio65 = GPIO_LEVEL_HIGH,
+	.gpio66 = GPIO_LEVEL_HIGH,
+	.gpio67 = GPIO_LEVEL_HIGH,
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio69 = GPIO_LEVEL_HIGH,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/clevo/w650sz/hda_verb.c b/src/mainboard/clevo/w650sz/hda_verb.c
new file mode 100644
index 0000000..0230a69
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/hda_verb.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x80862807, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+
+	0x00000002, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x0, 0x80860101),
+
+	/* NID 0x03.  */
+	AZALIA_PIN_CFG(0x0, 0x03, 0x18560010),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/clevo/w650sz/mainboard.c b/src/mainboard/clevo/w650sz/mainboard.c
new file mode 100644
index 0000000..aee0269
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/mainboard.c
@@ -0,0 +1,23 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_init(struct device *dev)
+{
+	pc_keyboard_init(NO_AUX_DEVICE);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = mainboard_init;
+
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
+			GMA_INT15_PANEL_FIT_DEFAULT,
+			GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/clevo/w650sz/romstage.c b/src/mainboard/clevo/w650sz/romstage.c
new file mode 100644
index 0000000..7a0011e
--- /dev/null
+++ b/src/mainboard/clevo/w650sz/romstage.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+	RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
+	RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
+	RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
+	RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
+	RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
+	RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
+	RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),
+	RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
+
+	RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+	RCBA_END_CONFIG,
+};
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+	struct pei_data pei_data = {
+		.pei_version = PEI_VERSION,
+		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
+		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = HPET_ADDR,
+		.rcba = (uintptr_t)DEFAULT_RCBA,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.temp_mmio_base = 0xfed08000,
+		.system_type = 0, /* Mobile */
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0xa0, 0, 0xa4, 0 },
+		.ec_present = 0,
+		.dimm_channel0_disabled = 0,
+		.dimm_channel1_disabled = 0,
+		.max_ddr3_freq = 1600,
+		.usb2_ports = {
+			/* Length, Enable, OCn#, Location */
+			{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+		},
+		.usb3_ports = {
+			{ 1, 0 },
+			{ 1, 0 },
+			{ 1, 1 },
+			{ 1, 1 },
+			{ 1, 2 },
+			{ 1, 2 },
+		},
+	};
+
+	struct romstage_params romstage_params = {
+		.pei_data = &pei_data,
+		.gpio_map = &mainboard_gpio_map,
+		.rcba_config = rcba_config,
+		.bist = bist,
+	};
+
+	romstage_common(&romstage_params);
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I84340af9490d1a48a9e7e1e98fefc646ced1d923
Gerrit-Change-Number: 33325
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) mytbk920423@gmail.com
Gerrit-Reviewer: Iru Cai mytbk920423@gmail.com
Gerrit-MessageType: newchange



    