Change in coreboot[master]: mb/intel/d510mo: Use common ramstage driver to configure the ck505

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21222

Change subject: mb/intel/d510mo: Use common ramstage driver to configure the ck505
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mb/intel/d510mo: Use common ramstage driver to configure the ck505

Untested.

Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e
Signed-off-by: Arthur Heymans 
---
M src/mainboard/intel/d510mo/Kconfig
M src/mainboard/intel/d510mo/devicetree.cb
M src/mainboard/intel/d510mo/romstage.c
3 files changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/21222/1

diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 0f747cc..b2ce4b6 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -28,6 +28,7 @@
    select INTEL_INT15
    select HAVE_OPTION_TABLE
    select HAVE_CMOS_DEFAULT
+	select DRIVERS_I2C_CK505

config MAX_CPUS
    int
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index c5b885f..eaae2e0 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -92,7 +92,18 @@
       end
       device pci 1f.1 off end
       device pci 1f.2 on end		# SATA
-      device pci 1f.3 on end		# SMbus
+      device pci 1f.3 on		# SMbus
+        chip drivers/i2c/ck505		# ICS9EPRS525 
+          register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
+                               0xff, 0xff, 0xff, 0xff,
+                               0xff, 0xff, 0xff, 0xff,
+                               0xff }"
+          register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff,
+                               0xff, 0x00, 0x00, 0x01,
+                               0x03, 0x25, 0x83, 0x17,
+                               0x0d }"
+        end
+      end
       device pci 1f.4 off end
       device pci 1f.5 off end
       device pci 1f.6 off end
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 502d220..c6406e6 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -102,9 +102,6 @@
 void mainboard_romstage_entry(unsigned long bist)
 {
    const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
-	const u8 clockgen_block[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00,
-					0x00, 0x01, 0x03, 0x25, 0x83, 0x17,
-					0x0d };
    int cbmem_was_initted;
    int s3resume = 0;
    int boot_path;
@@ -127,8 +124,6 @@

report_bist_failure(bist);
    enable_smbus();
-
-	smbus_block_write(0x69, 0, 13, clockgen_block);

pineview_early_initialization();