Change in coreboot[master]: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60320 )

Change subject: mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST
......................................................................

mb/google/brya: Change SD Card and Touch pad GPIO PAD_RST to RSMRST

When the GPIO is set as DEEP or PLTRST, the PAD_CFG_DW0 resets to default
state while the GPIO locking register gets a reset only in RSMRST which
prevents enumeration of SD card and Touch pad in warm reset.

Hence, change GPIO_PAD_RST to RSMRST to sync both the resets.

BUG:b:211573253
TEST=Boot to OS, issue warm reboot and see SD card and Touch pad
enumerating

Signed-off-by: Meera Ravindranath 
Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/60320/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index 0583930..e9a1299 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -84,9 +84,9 @@
    /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
    PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
    /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_B16, NONE, RSMRST, NF2),
    /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_B17, NONE, RSMRST, NF2),
    /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
    PAD_NC(GPP_B18, NONE),
    /* B19 : NC */
@@ -152,9 +152,9 @@
    /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
    PAD_CFG_GPO(GPP_D16, 0, DEEP),
    /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
-	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D17, NONE, RSMRST),
    /* D18 : UART1_TXD ==> SD_PE_RST_L */
-	PAD_CFG_GPO(GPP_D18, 1, DEEP),
+	PAD_CFG_GPO(GPP_D18, 1, RSMRST),
    /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
    PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),