Change in coreboot[master]: mb/intel/saddlebrook: drop it - coreboot-gerrit

22 Oct 2019

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36240 )
Change subject: mb/intel/saddlebrook: drop it
......................................................................
mb/intel/saddlebrook: drop it
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
Since no one could be found for testing this board it is assumed there
is no interest in keeping it, thus drop it. (see CB:35923)
Change-Id: Ib38fe3847b2166a53a8e105686370fa16b8131e6
Signed-off-by: Michael Niewöhner foss@mniewoehner.de
---
D src/mainboard/intel/saddlebrook/Kconfig
D src/mainboard/intel/saddlebrook/Kconfig.name
D src/mainboard/intel/saddlebrook/Makefile.inc
D src/mainboard/intel/saddlebrook/acpi/ec.asl
D src/mainboard/intel/saddlebrook/acpi/mainboard.asl
D src/mainboard/intel/saddlebrook/acpi/superio.asl
D src/mainboard/intel/saddlebrook/acpi_tables.c
D src/mainboard/intel/saddlebrook/board_info.txt
D src/mainboard/intel/saddlebrook/bootblock.c
D src/mainboard/intel/saddlebrook/cmos.default
D src/mainboard/intel/saddlebrook/cmos.layout
D src/mainboard/intel/saddlebrook/devicetree.cb
D src/mainboard/intel/saddlebrook/dsdt.asl
D src/mainboard/intel/saddlebrook/gpio.h
D src/mainboard/intel/saddlebrook/ramstage.c
D src/mainboard/intel/saddlebrook/romstage.c
D src/mainboard/intel/saddlebrook/spd/Makefile.inc
D src/mainboard/intel/saddlebrook/spd/spd.h
D src/mainboard/intel/saddlebrook/spd/spd_util.c
19 files changed, 0 insertions(+), 1,072 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36240/1

diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
deleted file mode 100644
index 934c15a..0000000
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2017 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_SKLSDLBRK
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_4096
-	select CONSOLE_SERIAL
-	select DRIVERS_UART
-	select GENERIC_SPD_BIN
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select SKYLAKE_SOC_PCH_H
-	select SOC_INTEL_SKYLAKE
-	select SUPERIO_NUVOTON_NCT6776
-	select SUPERIO_NUVOTON_NCT6776_COM_A
-	select HAVE_CMOS_DEFAULT
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select USE_INTEL_FSP_MP_INIT
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config MAINBOARD_DIR
-	string
-	default "intel/saddlebrook"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Skylake Saddle Brook"
-
-config MAINBOARD_FAMILY
-	string
-	default "Intel_SaddleBrook"
-
-config MAX_CPUS
-	int
-	default 8
-
-config TPM_PIRQ
-	hex
-	default 0x18  # GPP_E0_IRQ
-
-endif
diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name
deleted file mode 100644
index c85fb81..0000000
--- a/src/mainboard/intel/saddlebrook/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_SKLSDLBRK
-	bool "Skylake Saddle Brook"
diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc
deleted file mode 100644
index 683462b..0000000
--- a/src/mainboard/intel/saddlebrook/Makefile.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-## Copyright (C) 2016 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += spd
-
-bootblock-y += bootblock.c
-
-ramstage-y += ramstage.c
diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl
deleted file mode 100644
index e69de29..0000000
--- a/src/mainboard/intel/saddlebrook/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl
deleted file mode 100644
index 5174eeb..0000000
--- a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio.h>
diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl
deleted file mode 100644
index e69de29..0000000
--- a/src/mainboard/intel/saddlebrook/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c
deleted file mode 100644
index e69de29..0000000
--- a/src/mainboard/intel/saddlebrook/acpi_tables.c
+++ /dev/null
diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt
deleted file mode 100644
index d3295d9..0000000
--- a/src/mainboard/intel/saddlebrook/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Intel
-Board name: Saddle Brook Skylake Reference Board
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c
deleted file mode 100644
index cf9740d..0000000
--- a/src/mainboard/intel/saddlebrook/bootblock.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
-
-static void early_config_gpio(void)
-{
-	/* This is a hack for FSP because it does things in MemoryInit()
-	 * which it shouldn't do. We have to prepare certain gpios here
-	 * because of the brokenness in FSP. */
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void bootblock_mainboard_init(void)
-{
-	early_config_gpio();
-}
-
-void bootblock_mainboard_early_init(void)
-{
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/intel/saddlebrook/cmos.default b/src/mainboard/intel/saddlebrook/cmos.default
deleted file mode 100644
index 3296093..0000000
--- a/src/mainboard/intel/saddlebrook/cmos.default
+++ /dev/null
@@ -1,4 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-power_on_after_fail=Disable
-nmi=Enable
diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout
deleted file mode 100644
index 83a2e05..0000000
--- a/src/mainboard/intel/saddlebrook/cmos.layout
+++ /dev/null
@@ -1,117 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2016 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-# -----------------------------------------------------------------
-# Status Register A
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-#544        440       r       0        unused
-
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
deleted file mode 100644
index 3322bf8..0000000
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ /dev/null
@@ -1,295 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2017 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/skylake
-
-	# Enable deep Sx states
-	register "deep_s5_enable_ac" = "0"
-	register "deep_s5_enable_dc" = "0"
-	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
-
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
-	# FSP Configuration
-	register "EnableAzalia" = "1"
-	register "DspEnable" = "1"
-	register "IoBufferOwnership" = "3"
-	register "SmbusEnable" = "1"
-	register "ScsEmmcEnabled" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
-	register "SkipExtGfxScan" = "1"
-	register "Device4Enable" = "0"
-	register "Heci3Enabled" = "0"
-
-	register "SaGv" = "3"
-	register "PmTimerDisabled" = "0"
-
-	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
-	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
-	register "PmConfigSlpS3MinAssert" = "0x02"
-
-	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
-	register "PmConfigSlpS4MinAssert" = "0x04"
-
-	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
-	register "PmConfigSlpSusMinAssert" = "0x03"
-
-	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
-	register "PmConfigSlpAMinAssert" = "0x03"
-
-	register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
-	# VR Settings Configuration for 5 Domains
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	#| Psi1Threshold  | 20A   | 20A   | 20A         | 20A         | 20A   |
-	#| Psi2Threshold  | 4A    | 5A    | 5A          | 5A          | 5A    |
-	#| Psi3Threshold  | 1A    | 1A    | 1A          | 1A          | 1A    |
-	#| Psi3Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| Psi4Enable     | 1     | 1     | 1           | 1           | 1     |
-	#| ImonSlope      | 0     | 0     | 0           | 0           | 0     |
-	#| ImonOffset     | 0     | 0     | 0           | 0           | 0     |
-	#| IccMax         | 7A    | 34A   | 34A         | 35A         | 35A   |
-	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V       | 1.52V       | 1.52V |
-	#+----------------+-------+-------+-------------+-------------+-------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = 0x50, \
-		.psi2threshold = 0x10, \
-		.psi3threshold = 0x4, \
-		.psi3enable = 1, \
-		.psi4enable = 1, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0x1C, \
-		.voltage_limit = 0x5F0 \
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = 0x50, \
-		.psi2threshold = 0x14, \
-		.psi3threshold = 0x4, \
-		.psi3enable = 1, \
-		.psi4enable = 1, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0x88, \
-		.voltage_limit = 0x5F0 \
-	}"
-	register "domain_vr_config[VR_RING]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = 0x50, \
-		.psi2threshold = 0x14, \
-		.psi3threshold = 0x4, \
-		.psi3enable = 1, \
-		.psi4enable = 1, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0x88, \
-		.voltage_limit = 0x5F0, \
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = 0x50, \
-		.psi2threshold = 0x14, \
-		.psi3threshold = 0x4, \
-		.psi3enable = 1, \
-		.psi4enable = 1, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0x8C ,\
-		.voltage_limit = 0x5F0 \
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1, \
-		.psi1threshold = 0x50, \
-		.psi2threshold = 0x14, \
-		.psi3threshold = 0x4, \
-		.psi3enable = 1, \
-		.psi4enable = 1, \
-		.imon_slope = 0x0, \
-		.imon_offset = 0x0, \
-		.icc_max = 0x8C, \
-		.voltage_limit = 0x5F0 \
-	}"
-
-	# Enable x1 slot
-	register "PcieRpEnable[7]" = "1"
-	register "PcieRpClkReqSupport[7]" = "1"
-	register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
-
-	# Enable x4 slot
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpClkReqSupport[8]" = "1"
-	register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
-
-	# Enable Root port 6 and 13.
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[12]" = "1"
-
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[5]" = "1"
-	register "PcieRpClkReqSupport[12]" = "1"
-
-	# RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
-	register "PcieRpClkReqNumber[5]" = "0"
-	register "PcieRpClkReqNumber[12]" = "1"
-
-	register "EnableLan" = "1"
-
-	# USB related
-	register "SsicPortEnable" = "1"
-
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"  # OTG
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"  # Touch Pad
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"  # M.2 BT
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"  # Touch Panel
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"  # M.2 WWAN
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"  # Front Panel
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"  # Front Panel
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC2)"  # Stacked conn (lan + usb)
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"  # Stacked conn (lan + usb)
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC1)"  # LAN MAGJACK
-	register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
-	register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
-	register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
-	register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
-	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
-	register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
-	register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
-	register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
-
-	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
-
-	# Must leave UART0 enabled or SD/eMMC will not work as PCI
-
-	register "pirqa_routing" = "0x0b"
-	register "pirqb_routing" = "0x0a"
-	register "pirqc_routing" = "0x0b"
-	register "pirqd_routing" = "0x0b"
-	register "pirqe_routing" = "0x0b"
-	register "pirqf_routing" = "0x0b"
-	register "pirqg_routing" = "0x0b"
-	register "pirqh_routing" = "0x0b"
-
-	register "PmTimerDisabled" = "0"
-
-	register "EnableSata" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable" = "{ \
-		[0]	= 1, \
-		[1]	= 1, \
-		[2]	= 1, \
-		[3]	= 1, \
-		[4]	= 1, \
-		[5]	= 1, \
-		[6]	= 1, \
-		[7]	= 1, \
-	}"
-	register "SerialIoDevMode" = "{ \
-		[PchSerialIoIndexI2C0]	= PchSerialIoPci, \
-		[PchSerialIoIndexI2C1]	= PchSerialIoPci, \
-		[PchSerialIoIndexI2C2]	= PchSerialIoPci, \
-		[PchSerialIoIndexI2C3]	= PchSerialIoPci, \
-		[PchSerialIoIndexI2C4]	= PchSerialIoPci, \
-		[PchSerialIoIndexI2C5]	= PchSerialIoPci, \
-		[PchSerialIoIndexSpi0]	= PchSerialIoPci, \
-		[PchSerialIoIndexSpi1]	= PchSerialIoPci, \
-		[PchSerialIoIndexUart0]	= PchSerialIoPci, \
-		[PchSerialIoIndexUart1]	= PchSerialIoPci, \
-		[PchSerialIoIndexUart2]	= PchSerialIoSkipInit, \
-	}"
-
-	# PL2 override 25W
-	register "tdp_pl2_override" = "25"
-
-	# Send an extra VR mailbox command for the PS4 exit issue
-	register "SendVrMbxCmd" = "2"
-
-	# Use default SD card detect GPIO configuration
-	#register "sdcard_cd_gpio_default" = "GPP_A7"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 on  end # I2C #2
-		device pci 15.3 on  end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 17.0 on end # SATA
-		device pci 19.0 on  end # UART #2
-		device pci 19.1 on  end # I2C #5
-		device pci 19.2 on  end # I2C #4
-		device pci 1c.0 on  end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 off end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 on  end # UART #1
-		device pci 1e.2 on  end # GSPI #0
-		device pci 1e.3 on  end # GSPI #1
-		device pci 1e.4 off  end # eMMC
-		device pci 1e.5 off  end # SDIO
-		device pci 1e.6 off  end # SDCard
-		device pci 1f.0 on
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 on end # GbE
-	end
-end
diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl
deleted file mode 100644
index ac929a6..0000000
--- a/src/mainboard/intel/saddlebrook/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include <soc/intel/skylake/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
-
-	// CPU
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/skylake/acpi/systemagent.asl>
-			#include <soc/intel/skylake/acpi/pch.asl>
-		}
-	}
-
-	// Chipset specific sleep states
-	#include <soc/intel/skylake/acpi/sleepstates.asl>
-
-	// Mainboard specific
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h
deleted file mode 100644
index 98feea2..0000000
--- a/src/mainboard/intel/saddlebrook/gpio.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* EC in RW */
-#define GPIO_EC_IN_RW		GPP_C6
-
-/* BIOS Flash Write Protect */
-#define GPIO_PCH_WP		GPP_C23
-
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0	GPP_C12
-#define GPIO_MEM_CONFIG_1	GPP_C13
-#define GPIO_MEM_CONFIG_2	GPP_C14
-#define GPIO_MEM_CONFIG_3	GPP_C15
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE		GPE0_LAN_WAK
-
-/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
-#define GPE_WLAN_WAKE		GPE0_DW0_16
-
-/* Input device interrupt configuration */
-#define TOUCHPAD_INT_L		GPP_B3_IRQ
-#define TOUCHSCREEN_INT_L	GPP_E7_IRQ
-#define MIC_INT_L		GPP_F10_IRQ
-
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
-#define EC_SCI_GPI		GPE0_DW2_16
-#define EC_SMI_GPI		GPP_E15
-
-#ifndef __ACPI__
-/* Pad configuration in ramstage. */
-static const struct pad_config gpio_table[] = {
-/* EC_PCH_RCIN */	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LPC_LAD_0 */		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
-/* LPC_LAD_1 */		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
-/* LPC_LAD_2 */		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
-/* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
-/* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
-/* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
-/* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
-/* EC_LPC_CLK */	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
-/* EC_HID_INT */	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
-/* ISH_KB_PROX_INT */	PAD_CFG_GPI(GPP_A12, NONE, DEEP),
-/* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* PM_SUS_STAT */	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
-/* PCH_SUSACK */	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
-/* SD_1P8_SEL */
-/* SD_PWR_EN */
-/* ACCEL INTERRUPT */	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
-/* ISH_GP1 */		/* GPP_A19 */
-/* GYRO_DRDY */
-/* FLIP_ACCEL_INT */
-/* GYRO_INT */
-/* ISH_GP5 */		/* GPP_A23 */
-
-/* CORE_VID0 */		/* GPP_B0 */
-/* CORE_VID1 */		/* GPP_B1 */
-/* HSJ_MIC_DET */
-/* TRACKPAD_INT */			PAD_CFG_GPO(GPP_B3, 1, DEEP),
-/* BT_RF_KILL */	PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
-/* SRCCLKREQ0# */	/* GPP_B5 */
-/* WIFI_CLK_REQ */
-/* KEPLR_CLK_REQ */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-/* SRCCLKREQ3# */	/* GPP_B8 */
-/* SSD_CLK_REQ */
-/* SRCCLKREQ5# */	/* GPP_B10 */
-/* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
-/* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-/* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */	PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),
-/* GSPI0_CS# */		/* GPP_B15 */
-/* WLAN_PCIE_WAKE */
-/* SSD_PCIE_WAKE */	PAD_CFG_GPO(GPP_B17, 1, DEEP),
-/* GSPI0_MOSI */	/* GPP_B18 */
-/* CCODEC_SPI_CS */
-/* CODEC_SPI_CLK */
-/* CODEC_SPI_MISO */
-/* CODEC_SPI_MOSI */
-/* SM1ALERT# */		PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1),
-
-/* SMB_CLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-/* SMB_DATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-/* SMBALERT# */		PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1),
-/* M2_WWAN_PWREN */	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-/* SML0DATA */		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-/* SML0ALERT# */	/* GPP_C5 */
-/* EC_IN_RW */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-/* USB_CTL */		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
-/* UART0_RXD */		/* GPP_C8 */
-/* UART0_TXD */		/* GPP_C9 */
-/* NFC_RST* */
-/* EN_PP3300_KEPLER */
-/* PCH_MEM_CFG0 */
-/* PCH_MEM_CFG1 */
-/* PCH_MEM_CFG2 */
-/* PCH_MEM_CFG3 */
-/* I2C0_SDA */
-/* I2C0_SCL */
-/* I2C1_SDA */
-/* I2C1_SCL */
-/* GD_UART2_RXD */
-/* GD_UART2_TXD */
-/* TCH_PNL_PWREN */
-/* SPI_WP_STATUS */
-
-/* ITCH_SPI_CS */	/* GPP_D0 */
-/* ITCH_SPI_CLK */	/* GPP_D1 */
-/* ITCH_SPI_MISO_1 */	/* GPP_D2 */
-/* ITCH_SPI_MISO_0 */	/* GPP_D3 */
-/* CAM_FLASH_STROBE */
-/* EN_PP3300_DX_EMMC */
-/* EN_PP1800_DX_EMMC */
-/* SH_I2C1_SDA */
-/* SH_I2C1_SCL */
-/* TBD */
-/* USB_A0_ILIM_SEL */
-/* USB_A1_ILIM_SEL */
-/* EN_PP3300_DX_CAM */
-/* EN_PP1800_DX_AUDIO */
-/* ISH_UART0_TXD */	/* GPP_D14 */
-/* ISH_UART0_RTS */	/* GPP_D15 */
-/* ISH_UART0_CTS */	/* GPP_D16 */
-/* DMIC_CLK_1 */
-/* DMIC_DATA_1 */
-/* DMIC_CLK_0 */
-/* DMIC_DATA_0 */
-/* ITCH_SPI_D2 */	/* GPP_D21 */
-/* ITCH_SPI_D3 */	/* GPP_D22 */
-/* I2S_MCLK */
-
-/* SPI_TPM_IRQ */	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
-/* SATAXPCIE1 */	/* GPP_E1 */
-/* SSD_PEDET */
-/* CPU_GP0 */
-/* SSD_SATA_DEVSLP */	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
-/* SATA_DEVSLP1 */	/* GPP_E5 */
-/* SATA_DEVSLP2 */	/* GPP_E6 */
-/* TCH_PNL_INTR* */
-/* SATALED# */		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
-/* USB2_OC_0 */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
-/* USB2_OC_1 */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
-/* USB2_OC_2 */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
-/* USB2_OC_3 */		PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
-
-/* I2S2_SCLK */
-/* I2S2_SFRM */
-/* I2S2_TXD */		PAD_CFG_GPO(GPP_F2, 0, DEEP),
-/* I2S2_RXD */
-/* I2C2_SDA */		/* GPP_F4 */
-/* I2C2_SCL */		/* GPP_F5 */
-/* I2C3_SDA */		/* GPP_F6 */
-/* I2C3_SCL */		/* GPP_F7 */
-/* I2C4_SDA */
-/* I2C4_SDA */
-/* AUDIO_IRQ */
-/* I2C5_SCL */		/* GPP_F11 */
-/* EMMC_CMD */		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
-/* EMMC_DATA0 */	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-/* EMMC_DATA1 */	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
-/* EMMC_DATA2 */	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
-/* EMMC_DATA3 */	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-/* EMMC_DATA4 */	PAD_CFG_GPO(GPP_F17, 1, DEEP),
-/* EMMC_DATA5 */	PAD_CFG_GPO(GPP_F18, 1, DEEP),
-/* EMMC_DATA6 */	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-/* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
-/* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
-/* EMMC_CLK */		PAD_CFG_GPO(GPP_F22, 1, DEEP),
-			/* GPP_F23 */
-
-/* SD_CMD */		/* GPP_G0 */
-/* SD_DATA0 */
-/* SD_DATA1 */
-/* SD_DATA2 */
-/* SD_DATA3 */
-/* SD_CD# */
-/* SD_CLK */
-/* SD_WP */
-/* TBD */	PAD_CFG_GPO(GPP_G8, 1, DEEP),
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */	PAD_CFG_GPI(GPP_G23, NONE, DEEP),
-
-/* SD_CMD */		/* GPP_H0 */
-/* SD_DATA0 */
-/* SD_DATA1 */
-/* SD_DATA2 */
-/* SD_DATA3 */
-/* SD_CD# */
-/* SD_CLK */
-/* SD_WP */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */
-/* TBD */	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-/* TBD */	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-/* TBD */	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-/* TBD */	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-/* TBD */
-
-/* SD_CMD */		PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
-/* SD_CMD */		PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
-
-/* PCH_BATLOW */	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-/* EC_PCH_ACPRESENT */	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-/* EC_PCH_WAKE */	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
-/* EC_PCH_PWRBTN */	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
-/* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-/* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-			/* GPD7 */
-/* PM_SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* PCH_SLP_WLAN# */	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
-/* PM_SLP_S5# */	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
-/* LANPHYC */		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
-};
-
-/* Early pad configuration in romstage. */
-static const struct pad_config early_gpio_table[] = {
-/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
-};
-
-#endif
-
-#endif
diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c
deleted file mode 100644
index 42477e6..0000000
--- a/src/mainboard/intel/saddlebrook/ramstage.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/ramstage.h>
-#include "gpio.h"
-
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
-{
-	/* Configure pads prior to SiliconInit() in case there's any
-	 * dependencies during hardware initialization. */
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c
deleted file mode 100644
index 0ed6730..0000000
--- a/src/mainboard/intel/saddlebrook/romstage.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <fsp/api.h>
-#include <soc/gpio.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include "spd/spd.h"
-#include <spd_bin.h>
-
-
-void mainboard_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
-{
-	struct spd_block blk = {
-		.addr_map = { 0x50, 0x52, },
-	};
-
-	get_spd_smbus(&blk);
-	dump_spd_info(&blk);
-	printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
-
-	memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
-	memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
-	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
-		memory_params->MemorySpdPtr00);
-	printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
-		memory_params->MemorySpdPtr10);
-
-	/*
-	* Configure the DQ/DQS settings if required. In general the settings
-	* should be set in the FSP flash image and should not need to be
-	* changed.
-	*/
-	mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0,
-				   &memory_params->DqByteMapCh1);
-	mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0,
-				    &memory_params->DqsMapCpu2DramCh1);
-	mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
-	mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
-
-	/* update spd length*/
-	memory_params->MemorySpdDataLen = blk.len;
-	memory_params->DqPinsInterleaved = TRUE;
-}
diff --git a/src/mainboard/intel/saddlebrook/spd/Makefile.inc b/src/mainboard/intel/saddlebrook/spd/Makefile.inc
deleted file mode 100644
index 721736d..0000000
--- a/src/mainboard/intel/saddlebrook/spd/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-## Copyright (C) 2015 Intel Corporation.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd_util.c
diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h
deleted file mode 100644
index 70a1f68..0000000
--- a/src/mainboard/intel/saddlebrook/spd/spd.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define RCOMP_TARGET_PARAMS	0x5
-
-void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1);
-void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1);
-void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
-void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
-
-#endif
diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c
deleted file mode 100644
index a09cebc..0000000
--- a/src/mainboard/intel/saddlebrook/spd/spd_util.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include "spd.h"
-
-void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
-{
-	/* DQ byte map */
-	const u8 dq_map[2][12] = {
-		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
-		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
-		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
-		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
-	memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
-	memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
-}
-
-void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
-{
-	/* DQS CPU<>DRAM map */
-	const u8 dqs_map[2][8] = {
-		{ 0, 1, 3, 2, 4, 5, 6, 7 },
-		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
-	memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
-	memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
-}
-
-void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
-{
-	/* Rcomp resistor */
-	const u16 RcompResistor[3] = { 121, 81, 100 };
-	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
-}
-
-void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
-{
-	/* Rcomp target */
-	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
-		100, 40, 20, 20, 26 };
-	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
-}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib38fe3847b2166a53a8e105686370fa16b8131e6
Gerrit-Change-Number: 36240
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    