Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email )
Change subject: mb/google/rauru: Add EC suspend pin initial setting ......................................................................
mb/google/rauru: Add EC suspend pin initial setting
Set the EC suspend pin to output high.
TEST=Build pass, reboot pass, suspend/resume pass. BUG=b:395737458
Signed-off-by: Wenzhen Yu wenzhen.yu@mediatek.com Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/86381/1
diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 6a8431f..4385628 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -19,6 +19,7 @@ gpio_output(GPIO_EN_SPKR, 0); gpio_output(GPIO_FP_RST_1V8_S3_L, 0); gpio_output(GPIO_XHCI_INIT_DONE, 0); + gpio_output(GPIO_EC_SUSPEND_PIN, 1); }
void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index f35135c..a11097c 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -14,6 +14,7 @@ #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) +#define GPIO_EC_SUSPEND_PIN GPIO(EINT38) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) #define GPIO_BL_PWM_1V8 GPIO(DISP_PWM)