Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52982 )
Change subject: soc/amd/cezanne: Force resets to be cold ......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/52982/comment/d84a037d_fb1fca3d PS1, Line 10: /* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */ ppr says that's it's still valid; see LEGACYIOx000000F0 (FCH::IO::NCP_ERROR)
the warm reset flag only has informative character and from my understanding it shouldn't affect what the chipset does, but since i haven't verified that more than having a look at the ppr, i wouldn't bet on this. the one place where this is used is in cpu.c and mca.c which isn't implemented yet on cezanne and i'll improve the mca code on picasso before commonizing it. might be that the fsp writes to that register though
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Felix Held (Code Review)