HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40253 )
Change subject: sb/amd: Use 'const' to set pci_devfn_t statically ......................................................................
sb/amd: Use 'const' to set pci_devfn_t statically
Change-Id: Id4bfe74fab8917a52f518e86063ab0da2cf2680a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c 5 files changed, 9 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/40253/1
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index e103bc4..d8916ed 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -19,9 +19,7 @@ static void hudson_enable_rom(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_s_read_config8(dev, 0x48); diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a4399c9..46eea64 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -60,10 +60,9 @@ void hudson_lpc_port80(void) { u8 byte; - pci_devfn_t dev; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 7a1d05b..43d83f9 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -9,9 +9,8 @@ { u16 word; u32 dword; - pci_devfn_t dev; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
- dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. * BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT29: Port Enable for KBC port 0x60 and 0x64 @@ -43,7 +42,7 @@ static void enable_prefetch(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
/* Enable PrefetchEnSPIFromHost */ dword = pci_s_read_config32(dev, 0xb8); @@ -53,7 +52,7 @@ static void enable_spi_fast_mode(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
// set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index d0c3646..3231018 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -19,9 +19,7 @@ static void hudson_enable_rom(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_s_read_config8(dev, 0x48); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 126a85c..0eaf524 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -92,10 +92,9 @@ void hudson_lpc_port80(void) { u8 byte; - pci_devfn_t dev; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); @@ -227,7 +226,7 @@ static uintptr_t hudson_spibase(void) { /* Make sure the base address is predictable */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xfffffff0; @@ -280,7 +279,7 @@
void hudson_tpm_decode_spi(void) { - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40253 )
Change subject: sb/amd: Use 'const' to set pci_devfn_t statically ......................................................................
Patch Set 1:
The build failure looks unrelated.
abuild.xml.[failed-to-read]
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40253 )
Change subject: sb/amd: Use 'const' to set pci_devfn_t statically ......................................................................
Abandoned
splited
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HAOUAS Elyes (Code Review) -
Paul Menzel (Code Review)