build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27619 )
Change subject: amd/common/psp: Remove use of PspBaseLib ......................................................................
Patch Set 13:
(13 comments)
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... File src/soc/amd/common/block/include/amdblocks/psp.h:
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 26: #define PSP_PCI_MIRRORCTRL1_REG 0x44 /* PSP Mirror Reg Ctrl */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 27: #define PSP_PCI_EXTRAPCIHDR_REG 0x48 /* Extra PCI Header Ctrl */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 29: #define PCI_CONFIG_SMU_INDIRECT_INDEX 0xb8 /* GNB index for SMU mbox */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 30: #define PCI_CONFIG_SMU_INDIRECT_DATA 0xbc /* GNB data for SMU mbox */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 32: #define PCI_MAGIC_REG1 0xb8 /* PSP Mailbox MMIO control */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 33: #define PCI_MAGIC_REG2 0xbc /* PSP Mailbox MMIO control */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 35: #define MAGIC_ENABLE_BITS 0x34 /* Extra PCI HDR Ctl Enables */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 41: #define PMNXTPTRW_MASK 0xff /* PCI ACR MASK */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 42: #define PMNXTPTRW_EXPOSE 0xa4 /* Control val to expose the ACR */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 46: #define SMU_CC_PSP_FUSES_STATUS 0xc0018000ul /* GNB offset for PSP fusing */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 50: #define PSP_MAILBOX_BASE 0x70 /* Mailbox offset from PCIe BAR */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 52: #define MSR_CU_CBBCFG 0xc00110a2ul /* PSP Private Blk Base Addr */ line over 80 characters
https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/am... PS13, Line 53: #define BAR3HIDEBIT BIT(12) /* Bit to hide BAR3 addr if set */ line over 80 characters
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