Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: [WIP] mb/asus: Add Asus P8H61-M LX3 R2.0 ......................................................................
[WIP] mb/asus: Add Asus P8H61-M LX3 R2.0
Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality.
TODO: Test thoroughly, it currently boots and S3 resume works fine.
Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 14 files changed, 640 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39099/1
diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig new file mode 100644 index 0000000..03f1e8d --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8h61-m_lx3_r2_0 + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX3 R2.0" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name new file mode 100644 index 0000000..6d10dcf --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8H61_M_LX3_R2_0 + bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc new file mode 100644 index 0000000..7167e10 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl new file mode 100644 index 0000000..ab41034 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c new file mode 100644 index 0000000..23537a4 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt new file mode 100644 index 0000000..b889d3f --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb new file mode 100644 index 0000000..99b484c --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -0,0 +1,106 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + + register "pcie_port_coalesce" = "0" + + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3 + device pci 1c.3 on end # RP #4 + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl new file mode 100644 index 0000000..c92a550 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c new file mode 100644 index 0000000..6406d44 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Enable UART */ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads new file mode 100644 index 0000000..f12133b --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c new file mode 100644 index 0000000..f7f726a --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c new file mode 100644 index 0000000..6332289 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x10438415, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x585600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: [WIP] mb/asus: Add Asus P8H61-M LX3 R2.0 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/2/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c:
https://review.coreboot.org/c/coreboot/+/39099/2/src/mainboard/asus/p8h61-m_... PS2, Line 50: /* Enable UART */ You are a liar.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39099
to look at the new patch set (#3).
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
mb/asus/p8h61-m_lx3_r2_0: Add new mainboard
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality.
Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 14 files changed, 500 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39099/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/2/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c:
https://review.coreboot.org/c/coreboot/+/39099/2/src/mainboard/asus/p8h61-m_... PS2, Line 50: /* Enable UART */
You are a liar.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39099/3//COMMIT_MSG@27 PS3, Line 27: VBT Uh, I forgot to add it
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39099
to look at the new patch set (#4).
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
mb/asus/p8h61-m_lx3_r2_0: Add new mainboard
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality.
Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 15 files changed, 501 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39099/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39099/3//COMMIT_MSG@27 PS3, Line 27: VBT
Uh, I forgot to add it
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 4: Code-Review+1
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 4: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 20: select USE_NATIVE_RAMINIT do we want to force this as non-deselectable?
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 24: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> not needed for a desktop board w/only external display
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 20: select USE_NATIVE_RAMINIT
do we want to force this as non-deselectable?
It won't build though, non-native raminit needs an additional function to fill the pei_data struct.
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 24: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
not needed for a desktop board w/only external display
True, not anymore
Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Matt DeVillier, Paul Menzel, Arthur Heymans, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39099
to look at the new patch set (#5).
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
mb/asus/p8h61-m_lx3_r2_0: Add new mainboard
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality.
Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 15 files changed, 500 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39099/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 24: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
True, not anymore
Done
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG@22 PS5, Line 22: - Realtek GbE (coreboot must set the MAC address) assume this means via VPD or CBFS file?
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... File src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/39099/4/src/mainboard/asus/p8h61-m_... PS4, Line 20: select USE_NATIVE_RAMINIT
It won't build though, non-native raminit needs an additional function to fill the pei_data struct.
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG@22 PS5, Line 22: - Realtek GbE (coreboot must set the MAC address)
assume this means via VPD or CBFS file?
Yes, in this case via CBFS file that is created from Kconfig settings.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39099/5//COMMIT_MSG@22 PS5, Line 22: - Realtek GbE (coreboot must set the MAC address)
Yes, in this case via CBFS file that is created from Kconfig settings.
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39099 )
Change subject: mb/asus/p8h61-m_lx3_r2_0: Add new mainboard ......................................................................
mb/asus/p8h61-m_lx3_r2_0: Add new mainboard
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. Actually, I have the PLUS variant, but they use the same PCB. The only difference is the capacitor quality.
Working: - Both DIMM slots - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - Arch Linux using CorebootPayloadPkg
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig A src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name A src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c A src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt A src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt A src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb A src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl A src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c A src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads A src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c A src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c 15 files changed, 500 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig new file mode 100644 index 0000000..2fc0645 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig @@ -0,0 +1,34 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +if BOARD_ASUS_P8H61_M_LX3_R2_0 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NO_UART_ON_SUPERIO + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8h61-m_lx3_r2_0 + +config MAINBOARD_PART_NUMBER + string + default "P8H61-M LX3 R2.0" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name new file mode 100644 index 0000000..6d10dcf --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8H61_M_LX3_R2_0 + bool "P8H61-M LX3 R2.0" diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc new file mode 100644 index 0000000..7167e10 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/ec.asl diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl new file mode 100644 index 0000000..b84cada --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl new file mode 100644 index 0000000..bbab2af --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi/superio.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c new file mode 100644 index 0000000..3851d04 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt new file mode 100644 index 0000000..3e3c173 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/us/Motherboards/P8H61M_LX3_R20 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt b/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt new file mode 100644 index 0000000..e5be40c --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb new file mode 100644 index 0000000..6d91959 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x1043 0x844d inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 on end # RP #4: PCIEX1_1 + device pci 1c.4 on end # RP #5: PCIEX1_2 + device pci 1c.5 on end # RP #6: RTL8111 GbE NIC + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl new file mode 100644 index 0000000..af0cbad --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c new file mode 100644 index 0000000..e6f8186 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Do not enable UART, the header is not populated by default */ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads new file mode 100644 index 0000000..767f5af --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads @@ -0,0 +1,14 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (Analog, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c new file mode 100644 index 0000000..096ed43 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio57 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c new file mode 100644 index 0000000..cab7aa5 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x10438415, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438415), + AZALIA_PIN_CFG(0, 0x19, 0x410110f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19037), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x585600f0), + AZALIA_PIN_CFG(0, 0x21, 0x474411f0), + AZALIA_PIN_CFG(0, 0x22, 0x410160f0), + AZALIA_PIN_CFG(0, 0x23, 0x410120f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Matt DeVillier (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)