Change in coreboot[master]: [DNM] soc/intel: Fix SPI write protect and EISS support

[Benjamin Doron (Code Review)]

Attention is currently required from: Angel Pons, Patrick Rudolph.
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50724 )

Change subject: [DNM] soc/intel: Fix SPI write protect and EISS support
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50724/comment/12d0a5e6_96c2118f 
PS3, Line 9: Systems are hanging when chipset enforces SPI write protect.
> Even on vendor firmware I managed to lock up my HP 280 G2. […]

But that's not the issue here? coreboot can complete booting after enabling WP and setting the EISS and lock bits, but hangs in SMM when we have to enforce EISS.