Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69337 )
Change subject: soc/amd: Move "reset.c" to common ......................................................................
soc/amd: Move "reset.c" to common
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/soc/amd/cezanne/Makefile.inc R src/soc/amd/common/reset.c M src/soc/amd/glinda/Makefile.inc D src/soc/amd/glinda/reset.c M src/soc/amd/mendocino/Makefile.inc D src/soc/amd/mendocino/reset.c M src/soc/amd/morgana/Makefile.inc D src/soc/amd/morgana/reset.c M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/reset.c 10 files changed, 32 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/69337/1
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 1f2bb6d..bc2df40 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -12,18 +12,18 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c +bootblock-y += ../common/reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c +verstage_x86-y += ../common/reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c +romstage-y += ../common/reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -38,7 +38,7 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += preload.c -ramstage-y += reset.c +ramstage-y += ../common/reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/common/reset.c similarity index 99% rename from src/soc/amd/cezanne/reset.c rename to src/soc/amd/common/reset.c index 1360bd5..3598cab 100644 --- a/src/soc/amd/cezanne/reset.c +++ b/src/soc/amd/common/reset.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> #include <arch/io.h> #include <cf9_reset.h> #include <reset.h> #include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h>
void do_cold_reset(void) { diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index e00421d..e03ed67 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -15,19 +15,19 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c +bootblock-y += ../common/reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c +verstage_x86-y += ../common/reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c +romstage-y += ../common/reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -41,7 +41,7 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += preload.c -ramstage-y += reset.c +ramstage-y += ../common/reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/reset.c b/src/soc/amd/glinda/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/glinda/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 92c75f8..c3f7278 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -14,19 +14,19 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c +bootblock-y += ../common/reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c +verstage_x86-y += ../common/reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c +romstage-y += ../common/reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -40,7 +40,7 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += preload.c -ramstage-y += reset.c +ramstage-y += ../common/reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/mendocino/reset.c b/src/soc/amd/mendocino/reset.c deleted file mode 100644 index 28e60b6..0000000 --- a/src/soc/amd/mendocino/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a88e1a5..036e458 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -15,19 +15,19 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c +bootblock-y += ../common/reset.c bootblock-y += uart.c
verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c +verstage_x86-y += ../common/reset.c verstage_x86-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c +romstage-y += ../common/reset.c romstage-y += romstage.c romstage-y += uart.c
@@ -41,7 +41,7 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += preload.c -ramstage-y += reset.c +ramstage-y += ../common/reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/morgana/reset.c b/src/soc/amd/morgana/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/morgana/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ab18e3b..fc3ee11 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -12,19 +12,19 @@ bootblock-y += early_fch.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c +bootblock-y += ../common/reset.c bootblock-y += uart.c
romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c +romstage-y += ../common/reset.c romstage-y += romstage.c romstage-y += uart.c
verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c +verstage_x86-y += ../common/reset.c verstage_x86-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -38,7 +38,7 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += pcie_gpp.c -ramstage-y += reset.c +ramstage-y += ../common/reset.c ramstage-y += root_complex.c ramstage-y += sata.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c deleted file mode 100644 index 8181d90..0000000 --- a/src/soc/amd/picasso/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - /* TODO: Would a warm_reset() suffice? */ - do_cold_reset(); -}
-
Elyes Haouas (Code Review)