Change in coreboot[master]: nb/intel/x4x: Fix computing page_size

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22991

Change subject: nb/intel/x4x: Fix computing page_size
......................................................................

nb/intel/x4x: Fix computing page_size

This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD
decode and timing selection", but was probably not encountered because
such dimms are rather uncommon.

Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/22991/1

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 0b4d4a5..3cd75be 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -188,9 +188,10 @@
     * 1KB page size. For the x16 configuration, the page size is 2KB
     * for all densities except the 256Mb device, which has a 1KB page
     * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
+	 * The formula is pagesize in KiB = width * 2^col_bits / 8.
     */
-	s->dimms[dimm_idx].page_size = s->dimms[dimm_idx].width *
-		 (1 << decoded_dimm.col_bits);
+	s->dimms[dimm_idx].page_size = decoded_dimm.width *
+		 (1 << decoded_dimm.col_bits) / 8;

switch (decoded_dimm.banks) {
    case 4: