Change in coreboot[master]: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core

[Arthur Heymans (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Sridhar Siricilla, Michael Niewöhner, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )

Change subject: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core
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Patch Set 1:

(2 comments)

File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:

https://review.coreboot.org/c/coreboot/+/59359/comment/800d088f_4d0a476f 
PS1, Line 28: 	SFBC,	16,	// 0x48 - 0x49 Indicates Scaling factor for Big core
            : 	SFSC,	16,	// 0x50 - 0x51 Indicates Scaling Factor for Small Core
            : 	NMFQ,	16,	// 0x52 - 0x53 Indicates Nominal Frequency
            : 	CORE,	32,	// 0x54 - 0x57 Each marked bit indicates Big Core corresponding to core index
            : 	INFS,	8,	// 0x58 - Nominal Frequency is supported
            :
> but with coreboot producing AML at runtime, it is rarely actually required to use GNVS, and we prefer to keep away from that when possible. in this case, I don't think I see a good reason that it has to be in NVS.

Right, you can just define a namespace in the ssdt generator using acpigen_write_name_x

File src/soc/intel/common/block/acpi/cpu_hybrid.c:

https://review.coreboot.org/c/coreboot/+/59359/comment/bd7c24db_039390ce 
PS1, Line 66: pscope = (char *) malloc(12);
You can just allocate these on the stack. No need for malloc.