Change in coreboot[master]: riscv: add support to block smp in each stage

[Xiang Wang (Code Review)]

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/29024

to look at the new patch set (#3).

Change subject: riscv: add support to block smp in each stage
......................................................................

riscv: add support to block smp in each stage

Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/boot.c
M src/arch/riscv/bootblock.S
M src/arch/riscv/ramstage.S
M src/arch/riscv/stages.c
M src/soc/sifive/fu540/Kconfig
M src/soc/sifive/fu540/Makefile.inc
6 files changed, 19 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29024/3