Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19986 )
Change subject: soc/amd: Fix most checkpatch errors ......................................................................
soc/amd: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Changes to agesawrapper.c cause the build to change, so this file is also left as-is.
Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte().
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/agesawrapper.h M src/soc/amd/common/agesawrapper_call.h M src/soc/amd/common/amd_pci_util.c M src/soc/amd/common/amd_pci_util.h M src/soc/amd/common/cache_as_ram.inc M src/soc/amd/common/def_callouts.c M src/soc/amd/common/dimmSpd.h M src/soc/amd/common/heapmanager.c M src/soc/amd/common/spi.c M src/soc/amd/stoneyridge/acpi/fch.asl M src/soc/amd/stoneyridge/acpi/lpc.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/pci_int.asl M src/soc/amd/stoneyridge/acpi/pcie.asl M src/soc/amd/stoneyridge/acpi/usb.asl M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/dimmSpd.c M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/fadt.c M src/soc/amd/stoneyridge/fixme.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/hudson.c M src/soc/amd/stoneyridge/imc.c M src/soc/amd/stoneyridge/include/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/amd_pci_int_types.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/hudson.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/model_15_init.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sd.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/stoneyridge/uart.c 43 files changed, 800 insertions(+), 670 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19986/1
diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index ac953ca..886a602 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -20,7 +20,7 @@ #include <Porting.h> #include <AGESA.h>
-#define BIOS_HEAP_START_ADDRESS 0x010000000 +#define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000
@@ -38,21 +38,23 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); void EmptyHeap(void);
-AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_Reset(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, + VOID *ConfigPrt);
-AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, + VOID *ConfigPtr);
-AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS GetBiosCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
typedef struct { UINT32 CalloutName; diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index b7f60ad..36c91df 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -33,7 +33,7 @@ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_IVRS, /* IOMMU ACPI IVRS (I/O Virt. Reporting Structure) */ PICK_CRAT, };
@@ -45,7 +45,8 @@ AGESA_STATUS agesawrapper_amdinitmid(void); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, void *ConfigPtr); +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, + void *ConfigPtr); AGESA_STATUS agesawrapper_amdS3Save(void); AGESA_STATUS agesawrapper_amdinitresume(void); AGESA_STATUS agesawrapper_amds3laterestore(void); @@ -53,10 +54,10 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore(void); AGESA_STATUS agesawrapper_fchs3laterestore(void);
-VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); -const void *agesawrapper_locate_module (const CHAR8 name[8]); +const void *agesawrapper_locate_module(const CHAR8 name[8]);
void OemPostParams(AMD_POST_PARAMS *PostParams);
diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/agesawrapper_call.h index 925a424..64c97f6 100644 --- a/src/soc/amd/common/agesawrapper_call.h +++ b/src/soc/amd/common/agesawrapper_call.h @@ -30,14 +30,15 @@ * 0x6 = AGESA_CRITICAL * 0x7 = AGESA_FATAL */ -static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +static const char *decodeAGESA_STATUS(AGESA_STATUS sret) { - const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", + const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", "AGESA_BOUNDS_CHK", "AGESA_ALERT", "AGESA_WARNING", "AGESA_ERROR", "AGESA_CRITICAL", "AGESA_FATAL" }; - if (sret > 7) return "unknown"; /* Non-AGESA error code */ + if (sret > 7) + return "unknown"; /* Non-AGESA error code */ return statusStrings[sret]; }
diff --git a/src/soc/amd/common/amd_pci_util.c b/src/soc/amd/common/amd_pci_util.c index 1966541..0a7c8a1 100644 --- a/src/soc/amd/common/amd_pci_util.c +++ b/src/soc/amd/common/amd_pci_util.c @@ -22,12 +22,10 @@ #include <amd_pci_int_defs.h> #include <amd_pci_int_types.h>
-#ifndef __PRE_RAM__ - -const struct pirq_struct * pirq_data_ptr = NULL; +const struct pirq_struct *pirq_data_ptr = NULL; u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; +const u8 *intr_data_ptr = NULL; +const u8 *picr_data_ptr = NULL;
/* * Read the FCH PCI_INTR registers 0xC00/0xC01 at a @@ -54,35 +52,41 @@ * given in global variables intr_data and picr_data. * These variables are defined in mainboard.c */ -void write_pci_int_table (void) +void write_pci_int_table(void) { u8 byte;
- if (picr_data_ptr == NULL || intr_data_ptr == NULL){ - printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); + if (picr_data_ptr == NULL || intr_data_ptr == NULL) { + printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01" + " registers because\n" + "'mainboard_picr_data' or 'mainboard_intr_data'" + " tables are NULL\n"); return; }
/* PIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC" + " mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0 ; byte < FCH_INT_TABLE_SIZE ; byte++) { if (intr_types[byte]) { write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 0)); + byte, intr_types[byte], + read_pci_int_idx(byte, 0)); } }
/* APIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC" + " mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0 ; byte < FCH_INT_TABLE_SIZE ; byte++) { if (intr_types[byte]) { write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 1)); + byte, intr_types[byte], + read_pci_int_idx(byte, 1)); } } } @@ -94,29 +98,31 @@ */ void write_pci_cfg_irqs(void) { - device_t dev = NULL; /* Our current device to route IRQs to */ - device_t target_dev = NULL; /* The bridge that a device may be connected to */ - u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ - u16 target_pin = 0; /* Pin we will search our tables for */ - u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ - u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ - u16 devfn = 0; /* A PCI Device and Function number */ + device_t dev = NULL; /* Our current device to route IRQs */ + device_t target_dev = NULL; /* to bridge a device may be connected to */ + u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ + u16 target_pin = 0; /* Pin we will search our tables for */ + u16 int_line = 0; /* IRQ # read from PCI_INTR tbl and write to 3C */ + u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ + u8 bus = 0; /* A PCI Device Bus number */ + u16 devfn = 0; /* A PCI Device and Function number */ u8 bridged_device = 0; /* This device is on a PCI bridge */ u32 i = 0;
if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'mainboard_pirq_data' structure does not exist\n"); + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" + " because 'mainboard_pirq_data' structure does" + " not exist\n"); return; }
/* Populate the PCI cfg space header with the IRQ assignment */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ" + " assignments\n");
- for (dev = all_devices; dev; dev = dev->next) { + for (dev = all_devices ; dev ; dev = dev->next) { /* - * Step 1: Get the INT_PIN and device structure to look for in the + * Step 1: Get INT_PIN and device structure to look for in the * PCI_INTR table pirq_data */ target_dev = NULL; @@ -130,7 +136,7 @@ /* Get the original INT_PIN for record keeping */ int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (int_pin < 1 || int_pin > 4) - continue; /* Device has invalid INT_PIN so skip it */ + continue; /* Device has invalid INT_PIN - skip */
bus = target_dev->bus->secondary; devfn = target_dev->path.pci.devfn; @@ -139,14 +145,15 @@ * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR * register (0xC00) index for this device */ - pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ - for (i = 0; i < pirq_data_size; i++) { + pci_intr_idx = 0xbad; /* Will check to make sure it changed */ + for (i = 0 ; i < pirq_data_size ; i++) { if (pirq_data_ptr[i].devfn != devfn) continue;
- /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ + /* PIN_A is idx0 in pirq_data array but 1 in PCI reg */ pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; - printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); + printk(BIOS_SPEW, "\tFound this device in pirq_data" + " table entry %d\n", i); break; }
@@ -154,22 +161,32 @@ * Step 3: Make sure we got a valid index and use it to get * the IRQ number from the PCI_INTR register table */ - if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ - printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); + if (pci_intr_idx == 0xbad) { + /* Not on a bridge or in pirq_data table, skip it */ + printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in" + " pirq_data table\n", devfn); continue; - } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ - printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); + } else if (pci_intr_idx == 0x1f) { + /* Index found is not defined */ + printk(BIOS_SPEW, "Got index 0x1F (Not Connected)," + " perhaps this device was" + " defined wrong?\n"); continue; - } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", - __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); + } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { + /* Index out of bounds */ + printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index" + " 0x%x, max is 0x%x\n", __func__, + pci_intr_idx, FCH_INT_TABLE_SIZE); continue; }
- /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ + /* Find the value to program into the INT_LINE register from + * the PCI_INTR registers + */ int_line = read_pci_int_idx(pci_intr_idx, 0); if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ - printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); + printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps" + " this device was defined wrong?\n"); continue; }
@@ -180,7 +197,7 @@ */ pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line);
- /* Set this IRQ to level triggered since it is used by a PCI device */ + /* Set IRQ to level triggered since used by a PCI device */ i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
/* @@ -190,11 +207,12 @@ int_pin, pin_to_str(int_pin)); if (bridged_device) printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); + target_pin, pin_to_str(target_pin)); printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + pci_intr_idx, intr_types[pci_intr_idx], + int_line, int_line); } /* for (dev = all_devices) */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space" + " IRQ assignments\n"); } -#endif /* __PRE_RAM__ */ diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/amd_pci_util.h index fd5f077..4789542 100644 --- a/src/soc/amd/common/amd_pci_util.h +++ b/src/soc/amd/common/amd_pci_util.h @@ -28,14 +28,14 @@ u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ };
-extern const struct pirq_struct * pirq_data_ptr; +extern const struct pirq_struct *pirq_data_ptr; extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; +extern const u8 *intr_data_ptr; +extern const u8 *picr_data_ptr;
u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); void write_pci_cfg_irqs(void); -void write_pci_int_table (void); +void write_pci_int_table(void);
#endif /* AMD_PCI_UTIL_H */ diff --git a/src/soc/amd/common/cache_as_ram.inc b/src/soc/amd/common/cache_as_ram.inc index c0a69ec..7c8da8f 100644 --- a/src/soc/amd/common/cache_as_ram.inc +++ b/src/soc/amd/common/cache_as_ram.inc @@ -64,7 +64,7 @@ AMD_ENABLE_STACK
/* Align the stack. */ - and $0xFFFFFFF0, %esp + and $0xfffffff0, %esp
#ifdef __x86_64__ /* switch to 64 bit long mode */ diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index 52b502c..fa0d0c1 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -23,32 +23,33 @@ #include <agesawrapper.h> #include <BiosCallOuts.h> #include <dimmSpd.h> +#include <soc/hudson.h>
-AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS GetBiosCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINTN i;
- for (i = 0; i < BiosCalloutsLen; i++) { + for (i = 0 ; i < BiosCalloutsLen ; i++) { if (BiosCallouts[i].CalloutName == Func) break; } if (i >= BiosCalloutsLen) return AGESA_UNSUPPORTED;
- return BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return BiosCallouts[i].CalloutPtr(Func, Data, ConfigPtr); }
-AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { return AGESA_UNSUPPORTED; }
-AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { return AGESA_SUCCESS; }
-AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { IDS_NV_ITEM *IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; if (Data == IDS_CALLOUT_INIT) @@ -56,23 +57,22 @@ return AGESA_SUCCESS; }
-AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_Reset(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; - AMD_CONFIG_PARAMS *StdHeader; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; StdHeader = ConfigPtr;
- // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // + /* Perform the RESET based upon the ResetType. In case of + * WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to + * AmdResetManager. During the critical condition, where reset is + * required immediately, the reset will be invoked directly by writing + * 0x04 to port 0xCF9 (Reset Port). + */ switch (ResetType) { case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: @@ -81,7 +81,7 @@ case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader); break;
default: @@ -92,29 +92,33 @@ return Status; }
-AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
- Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + Status = agesawrapper_amdlaterunaptask(Func, Data, ConfigPtr); return Status; }
-AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, + VOID *ConfigPrt) { - GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; + + pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); - printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr); - return (pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING); + printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", + pVbiosImageInfo->ImagePtr); + return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; }
-AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status = AGESA_UNSUPPORTED; #ifdef __PRE_RAM__ - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + Status = AmdMemoryReadSPD(Func, Data, ConfigPtr); #endif return Status; } @@ -122,6 +126,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status = AGESA_UNSUPPORTED; + #ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; if (info->MemChannelId > 0) @@ -132,7 +137,7 @@ return AGESA_UNSUPPORTED;
/* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, 0) < 0) die("No SPD data\n");
Status = AGESA_SUCCESS; diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h index 1ad4546..3f34861 100644 --- a/src/soc/amd/common/dimmSpd.h +++ b/src/soc/amd/common/dimmSpd.h @@ -17,7 +17,8 @@ #define _DIMMSPD_H_
AGESA_STATUS -AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); +AmdMemoryReadSPD(IN UINT32 Func, IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData);
int hudson_readSpd(int spdAddress, char *buf, size_t len); int smbus_readSpd(int spdAddress, char *buf, size_t len); diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index b733fe8..4aedb19 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -25,14 +25,14 @@ UINT32 heap = BIOS_HEAP_START_ADDRESS;
if (acpi_is_wakeup_s3()) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH);
return heap; }
void EmptyHeap(void) { - void *BiosManagerPtr = (void *) GetHeapBase(NULL); + void *BiosManagerPtr = (void *)GetHeapBase(NULL); memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); }
@@ -54,26 +54,32 @@ BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams;
- AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams = ((AGESA_BUFFER_PARAMS *)ConfigPtr); AllocParams->BufferPointer = NULL;
AvailableHeapSize = BIOS_HEAP_SIZE - sizeof(BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr;
if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ CurrNodeOffset = sizeof(BIOS_HEAP_MANAGER); - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + CurrNodeOffset); CurrNodePtr->BufferHandle = AllocParams->BufferHandle; CurrNodePtr->BufferSize = AllocParams->BufferLength; CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof(BIOS_BUFFER_NODE); + AllocParams->BufferPointer = (UINT8 *)CurrNodePtr + + sizeof(BIOS_BUFFER_NODE);
/* Update the remaining free space */ - FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof(BIOS_BUFFER_NODE); - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - FreedNodePtr->BufferSize = AvailableHeapSize - sizeof(BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + + sizeof(BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize + - sizeof(BIOS_BUFFER_NODE) + - CurrNodePtr->BufferSize; FreedNodePtr->NextNodeOffset = 0;
/* Update the offsets for Allocated and Freed nodes */ @@ -84,16 +90,20 @@ * If it has, return AGESA_BOUNDS_CHK. */ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + CurrNodeOffset);
while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == + AllocParams->BufferHandle) { return AGESA_BOUNDS_CHK; } CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - * to the end of the allocated nodes list. + /* If BufferHandle has not been allocated on the heap, + * CurrNodePtr here points to the end of the allocated + * nodes list. */ } /* Find the node that best fits the requested buffer size */ @@ -101,8 +111,9 @@ PrevNodeOffset = FreedNodeOffset; BestFitNodeOffset = 0; BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + while (FreedNodeOffset != 0) { /* todo: simplify this */ + FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + FreedNodeOffset); if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) { if (BestFitNodeOffset == 0) { /* First node that fits the requested buffer size */ @@ -110,7 +121,7 @@ BestFitPrevNodeOffset = PrevNodeOffset; } else { /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitNodeOffset); if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { BestFitNodeOffset = FreedNodeOffset; BestFitPrevNodeOffset = PrevNodeOffset; @@ -122,43 +133,64 @@ } /* end of while loop */
if (BestFitNodeOffset == 0) { - /* If we could not find a node that fits the requested buffer - * size, return AGESA_BOUNDS_CHK. + /* If we could not find a node that fits the requested + * buffer size, return AGESA_BOUNDS_CHK. */ return AGESA_BOUNDS_CHK; } else { - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) + (BiosHeapBaseAddr + + BestFitPrevNodeOffset);
- /* If BestFitNode is larger than the requested buffer, fragment the node further */ - if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE); + /* If BestFitNode is larger than the requested buffer, + * fragment the node further + */ + if (BestFitNodePtr->BufferSize > + (AllocParams->BufferLength + + sizeof(BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + + AllocParams->BufferLength + + sizeof(BIOS_BUFFER_NODE);
- NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + NextFreePtr = (BIOS_BUFFER_NODE *) + (BiosHeapBaseAddr + + NextFreeOffset); + NextFreePtr->BufferSize = + BestFitNodePtr->BufferSize + - (AllocParams->BufferLength + + sizeof(BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = + BestFitNodePtr->NextNodeOffset; } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + /* Otherwise, next free node is + * NextNodeOffset of BestFitNode + */ NextFreeOffset = BestFitNodePtr->NextNodeOffset; }
- /* If BestFitNode is the first buffer in the list, then update - * StartOfFreedNodes to reflect the new free node. + /* If BestFitNode is the first buffer in the list, then + * update StartOfFreedNodes to reflect new free node. */ - if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; - } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; - } + if (BestFitNodeOffset == + BiosHeapBasePtr->StartOfFreedNodes) + BiosHeapBasePtr->StartOfFreedNodes = + NextFreeOffset; + else + BestFitPrevNodePtr->NextNodeOffset = + NextFreeOffset;
/* Add BestFitNode to the list of Allocated nodes */ CurrNodePtr->NextNodeOffset = BestFitNodeOffset; BestFitNodePtr->BufferSize = AllocParams->BufferLength; - BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->BufferHandle = + AllocParams->BufferHandle; BestFitNodePtr->NextNodeOffset = 0;
/* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof(BIOS_BUFFER_NODE); + AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr + + sizeof(BIOS_BUFFER_NODE); } }
@@ -181,50 +213,57 @@ BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams;
- AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + AllocParams = (AGESA_BUFFER_PARAMS *)ConfigPtr;
- BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr;
/* Find target node to deallocate in list of allocated nodes. * Return AGESA_BOUNDS_CHK if the BufferHandle is not found. */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset;
- while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) return AGESA_BOUNDS_CHK; - } PrevNodeOffset = AllocNodeOffset; AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + AllocNodeOffset); }
/* Remove target node from list of allocated nodes */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + PrevNodeOffset); PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
/* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + LibAmdMemFill((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, + AllocNodePtr->BufferSize, + &(AllocParams->StdHeader)); AllocNodePtr->BufferHandle = 0; AllocNodePtr->BufferSize += sizeof(BIOS_BUFFER_NODE);
/* Add deallocated node in order to the list of freed nodes */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + FreedNodeOffset);
EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
if (AllocNodeOffset < FreedNodeOffset) { /* Add to the start of the freed list */ if (EndNodeOffset == FreedNodeOffset) { - /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + /* If the freed node is adjacent to the first node in + * the list, concatenate both nodes + */ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + AllocNodePtr->NextNodeOffset = + FreedNodePtr->NextNodeOffset;
- /* Clear the BufferSize and NextNodeOffset of the previous first node */ + /* Clear the BufferSize and NextNodeOffset of the + * previous first node + */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0;
@@ -238,8 +277,8 @@ /* Update StartOfFreedNodes to the new first node */ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { - /* Traverse list of freed nodes to find where the deallocated node - * should be placed. + /* Traverse list of freed nodes to find where the deallocated + * node should be placed. */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; @@ -249,30 +288,36 @@ break; } NextNodeOffset = NextNodePtr->NextNodeOffset; - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + NextNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + NextNodeOffset); }
/* If deallocated node is adjacent to the next node, * concatenate both nodes. */ if (NextNodeOffset == EndNodeOffset) { - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + NextNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + NextNodeOffset); AllocNodePtr->BufferSize += NextNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + AllocNodePtr->NextNodeOffset = + NextNodePtr->NextNodeOffset;
NextNodePtr->BufferSize = 0; NextNodePtr->NextNodeOffset = 0; } else { - /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + /*AllocNodePtr->NextNodeOffset = + * FreedNodePtr->NextNodeOffset; */ AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, * concatenate both nodes. */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->NextNodeOffset = + AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
AllocNodePtr->BufferSize = 0; @@ -288,17 +333,17 @@ { UINT32 AllocNodeOffset; UINT8 *BiosHeapBaseAddr; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams;
- AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + AllocParams = (AGESA_BUFFER_PARAMS *)ConfigPtr;
- BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr;
AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset);
while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { @@ -307,11 +352,13 @@ return AGESA_BOUNDS_CHK; } else { AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + + AllocNodeOffset); } }
- AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); + AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr + + sizeof(BIOS_BUFFER_NODE)); AllocParams->BufferLength = AllocNodePtr->BufferSize;
return AGESA_SUCCESS; diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/spi.c index ce6deef..31b686d 100644 --- a/src/soc/amd/common/spi.c +++ b/src/soc/amd/common/spi.c @@ -36,6 +36,4 @@ spi_flash_write(flash, pos + sizeof(len), len, buf);
spi_flash_volatile_group_end(flash); - - return; } diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl index df9caac..1e0c889 100644 --- a/src/soc/amd/stoneyridge/acpi/fch.asl +++ b/src/soc/amd/stoneyridge/acpi/fch.asl @@ -72,38 +72,38 @@ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, /* address granularity */ 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ + 0x00ff, /* range maximum */ 0x0000, /* translation */ 0x0100, /* length */ ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ + 0x0cf7, /* range maximum */ 0x0000, /* translation */ - 0x0CF8 /* length */ + 0x0cf8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ - 0x03B0, /* range minimum */ - 0x03DF, /* range maximum */ + 0x03b0, /* range minimum */ + 0x03df, /* range maximum */ 0x0000, /* translation */ 0x0030 /* length */ )
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ + 0x0d00, /* range minimum */ + 0xffff, /* range maximum */ 0x0000, /* translation */ - 0xF300 /* length */ + 0xf300 /* length */ )
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index 6332d47..783a2c9 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -76,7 +76,7 @@ Name(_CRS, ResourceTemplate() { IRQNoFlags(){2} IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) + IO(Decode16,0x00a0, 0x00a0, 0, 2) }) } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
@@ -88,15 +88,15 @@ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + IO(Decode16, 0x008f, 0x008f, 0x01, 0x01) + IO(Decode16, 0x00c0, 0x00c0, 0x10, 0x20) }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
Device(COPR) { Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IO(Decode16, 0x00f0, 0x00f0, 0, 0x10) IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c5876ff..9cc8ff0 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -118,7 +118,7 @@ MMLA, 32, offset (0x68), MMHA, 32, - offset (0x6C), + offset (0x6c), MMDT, 16, }
diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 52e9e28..617b9eb 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -33,14 +33,14 @@ PT7D, 1, PT8D, 1, PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + Offset(0x000a0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ SBIE, 1, SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + Offset(0x000a0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + Offset(0x000a0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + Offset(0x000a0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ ,14, P92E, 1, /* Port92 decode enable */ } @@ -58,26 +58,26 @@ P0DD, 4, , 4, P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ + Offset(0x12c), /* Port 0 Serial ATA control */ P0DI, 4, Offset(0x130), /* Port 0 Serial ATA error */ , 16, P0PR, 1,
/* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ + offset(0x1a0), /* Port 1 Task file status */ P1ER, 1, , 2, P1DQ, 1, , 3, P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ + Offset(0x1a8), /* Port 1 Serial ATA status */ P1DD, 4, , 4, P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ + Offset(0x1ac), /* Port 1 Serial ATA control */ P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ + Offset(0x1b0), /* Port 1 Serial ATA error */ , 16, P1PR, 1,
@@ -92,26 +92,26 @@ P2DD, 4, , 4, P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ + Offset(0x22c), /* Port 2 Serial ATA control */ P2DI, 4, Offset(0x230), /* Port 2 Serial ATA error */ , 16, P2PR, 1,
/* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ + Offset(0x2a0), /* Port 3 Task file status */ P3ER, 1, , 2, P3DQ, 1, , 3, P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ + Offset(0x2a8), /* Port 3 Serial ATA status */ P3DD, 4, , 4, P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ + Offset(0x2aC), /* Port 3 Serial ATA control */ P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ + Offset(0x2b0), /* Port 3 Serial ATA error */ , 16, P3PR, 1, } @@ -146,7 +146,7 @@
Method(_STA, 0) { if (PIRA) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -187,7 +187,7 @@
Method(_STA, 0) { if (PIRB) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -228,7 +228,7 @@
Method(_STA, 0) { if (PIRC) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -269,7 +269,7 @@
Method(_STA, 0) { if (PIRD) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -310,7 +310,7 @@
Method(_STA, 0) { if (PIRE) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -351,7 +351,7 @@
Method(_STA, 0) { if (PIRF) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -392,7 +392,7 @@
Method(_STA, 0) { if (PIRG) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } @@ -433,7 +433,7 @@
Method(_STA, 0) { if (PIRH) { - Return(0x0B) /* sata is invisible */ + Return(0x0b) /* sata is invisible */ } else { Return(0x09) /* sata is disabled */ } diff --git a/src/soc/amd/stoneyridge/acpi/pcie.asl b/src/soc/amd/stoneyridge/acpi/pcie.asl index adb5c4d..9251872 100644 --- a/src/soc/amd/stoneyridge/acpi/pcie.asl +++ b/src/soc/amd/stoneyridge/acpi/pcie.asl @@ -14,7 +14,7 @@ */
/* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) Field(PRQM, ByteAcc, NoLock, Preserve) { PRQI, 0x00000008, PRQD, 0x00000008, /* Offset: 1h */ @@ -31,7 +31,7 @@ }
/* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001) Field(PERC, ByteAcc, NoLock, Preserve) { SENS, 0x00000001, PENS, 0x00000001, @@ -40,7 +40,7 @@ }
/* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { CMTI, 8, /* Client Management Data register */ @@ -52,7 +52,7 @@ }
/* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001) Field(GPT, ByteAcc, NoLock, Preserve) { GPB0,1, GPB1,1, @@ -65,21 +65,21 @@ }
/* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { , 0x00000006, FLRE, 0x00000001, }
/* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002) Field(PM2R, ByteAcc, NoLock, Preserve) { PM2I, 0x00000008, PM2D, 0x00000008, }
/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002) Field(PIOR, ByteAcc, NoLock, Preserve) { PIOI, 0x00000008, PIOD, 0x00000008, @@ -88,7 +88,7 @@ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { Offset(0x60), /* AcpiPm1EvgBlk */ P1EB, 16, - Offset(0xEE), + Offset(0xee), UPWS, 3, } OperationRegion (P1E0, SystemIO, P1EB, 0x04) diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl index fd3ff54..b2e5f49 100644 --- a/src/soc/amd/stoneyridge/acpi/usb.asl +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -17,49 +17,49 @@ /* 0:12.0 - OHCI */ Device(UOH1) { Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH1 */
/* 0:12.2 - EHCI */ Device(UOH2) { Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH2 */
/* 0:13.0 - OHCI */ Device(UOH3) { Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH3 */
/* 0:13.2 - EHCI */ Device(UOH4) { Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH4 */
/* 0:16.0 - OHCI */ Device(UOH5) { Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH5 */
/* 0:16.2 - EHCI */ Device(UOH6) { Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) + Name(_PRW, Package() {0x0b, 3}) } /* end UOH5 */
/* 0:10.0 - XHCI 0*/ Device(XHC0) { Name(_ADR, 0x00100000) - Name(_PRW, Package() {0x0B, 4}) + Name(_PRW, Package() {0x0b, 4}) } /* end XHC0 */
#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) - Name(_PRW, Package() {0x0B, 4}) + Name(_PRW, Package() {0x0b, 4}) } /* end XHC1 */ #endif diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 32b1298..9223302 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -31,7 +31,7 @@ u8 reg8; pci_devfn_t dev;
- dev = PCI_DEV(0, 0x14, 3); + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
/* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_io_read_config8(dev, 0x48); @@ -52,7 +52,8 @@ * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 + - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ pci_io_write_config16(dev, 0x6e, 0xffff); } diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index c319001..7b36a64 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -56,13 +56,12 @@ }
/* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { + if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { + else if (dev->path.type == DEVICE_PATH_PCI) hudson_enable(dev); - } }
static void soc_init(void *chip_info) diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index f913b05..747c295 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -18,8 +18,7 @@
#include <stdint.h>
-struct soc_amd_stoneyridge_config -{ +struct soc_amd_stoneyridge_config { u8 spdAddrLookup[1][1][2]; u32 ide0_enable : 1; u32 sata0_enable : 1; diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c index 80fe12d..cb39bdb 100644 --- a/src/soc/amd/stoneyridge/dimmSpd.c +++ b/src/soc/amd/stoneyridge/dimmSpd.c @@ -24,25 +24,26 @@ #include "chip.h" #include <dimmSpd.h>
-AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINT32 unused2, + AGESA_READ_SPD_PARAMS *info) { int spdAddress; DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - DEVTREE_CONST struct soc_amd_stoneyridge_config *config = dev->chip_info; + DEVTREE_CONST struct soc_amd_stoneyridge_config *conf = dev->chip_info;
- if ((dev == 0) || (config == 0)) + if ((dev == 0) || (conf == 0)) return AGESA_ERROR; - if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + if (info->SocketId >= ARRAY_SIZE(conf->spdAddrLookup)) return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + if (info->MemChannelId >= ARRAY_SIZE(conf->spdAddrLookup[0])) return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + if (info->DimmId >= ARRAY_SIZE(conf->spdAddrLookup[0][0])) return AGESA_ERROR; - spdAddress = config->spdAddrLookup - [info->SocketId] [info->MemChannelId] [info->DimmId]; + spdAddress = conf->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 9bca381..d3c9dd2 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -34,9 +34,11 @@ { u8 byte;
- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * 2); byte |= 1 << 3; - write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * 2, byte); byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); byte |= 1 << 3; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); @@ -46,7 +48,9 @@ write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
udelay(2000); - write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ + /* reset UART */ + write8((void *)APU_UART0_BASE + (0x2000 * CONFIG_UART_FOR_CONSOLE) + + 0x88, 0x01); }
void hudson_pci_port80(void) @@ -55,7 +59,7 @@ pci_devfn_t dev;
/* P2P Bridge */ - dev = PCI_DEV(0, 0x14, 4); + dev = PCI_DEV(0, SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC);
/* Chip Control: Enable subtractive decoding */ byte = pci_read_config8(dev, 0x40); @@ -63,23 +67,23 @@ pci_write_config8(dev, 0x40, byte);
/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ - byte = pci_read_config8(dev, 0x4B); + byte = pci_read_config8(dev, 0x4b); byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); + pci_write_config8(dev, 0x4b, byte);
/* The same IO Base and IO Limit here is meaningful because we set the * bridge to be subtractive. During early setup stage, we have to make * sure that data can go through port 0x80. */ /* IO Base: 0xf000 */ - byte = pci_read_config8(dev, 0x1C); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1C, byte); + byte = pci_read_config8(dev, 0x1c); + byte |= 0xf << 4; + pci_write_config8(dev, 0x1c, byte);
/* IO Limit: 0xf000 */ - byte = pci_read_config8(dev, 0x1D); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1D, byte); + byte = pci_read_config8(dev, 0x1d); + byte |= 0xf << 4; + pci_write_config8(dev, 0x1d, byte);
/* PCI Command: Enable IO response */ byte = pci_read_config8(dev, 0x04); @@ -87,11 +91,11 @@ pci_write_config8(dev, 0x04, byte);
/* LPC controller */ - dev = PCI_DEV(0, 0x14, 3); + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
- byte = pci_read_config8(dev, 0x4A); + byte = pci_read_config8(dev, 0x4a); byte &= ~(1 << 5); /* disable lpc port 80 */ - pci_write_config8(dev, 0x4A, byte); + pci_write_config8(dev, 0x4a, byte); }
void hudson_lpc_port80(void) @@ -100,14 +104,14 @@ pci_devfn_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); + outb(0xec, PM_INDEX); + byte = inb(PM_DATA); byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + outb(0xec, PM_INDEX); + outb(byte, PM_DATA);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3); + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); @@ -191,17 +195,17 @@ /* Find and open Base Register and program it */ tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT);
- if ((tmp & 0xFFFF) == 0) { /* WIDEIO0 */ + if ((tmp & 0xffff) == 0) { /* WIDEIO0 */ tmp |= base; pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); enable_wideio(0, size); - } else if ((tmp & 0xFFFF0000) == 0) { /* WIDEIO1 */ + } else if ((tmp & 0xffff0000) == 0) { /* WIDEIO1 */ tmp |= (base << 16); pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); enable_wideio(1, size); } else { /* Check WIDEIO2 register */ tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT); - if ((tmp & 0xFFFF) == 0) { /* WIDEIO2 */ + if ((tmp & 0xffff) == 0) { /* WIDEIO2 */ tmp |= base; pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); enable_wideio(2, size); @@ -226,11 +230,12 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", + dword, size, nvram_pos);
- for (i = 0; i < size; i++) { + for (i = 0 ; i < size ; i++) { outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); nvram_pos++; }
@@ -241,15 +246,15 @@ { u32 data = *old_dword; int i; - for (i = 0; i < size; i++) { + for (i = 0 ; i < size ; i++) { outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); + data |= inb(BIOSRAM_DATA) << (i * 8); nvram_pos++; } *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, - nvram_pos-size); + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", + *old_dword, size, nvram_pos-size); return nvram_pos; }
@@ -261,7 +266,7 @@ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); + memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40); data = *memptr;
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ @@ -272,11 +277,11 @@ static uintptr_t hudson_spibase(void) { /* Make sure the base address is predictable */ - device_t dev = PCI_DEV(0, 0x14, 3); + device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xfffffff0; - if (!base){ + if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base | SPI_ROM_ENABLE); @@ -324,7 +329,7 @@
void hudson_tpm_decode_spi(void) { - device_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */ + device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */
u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index dc09b85..675f4b7 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -55,5 +55,6 @@ outb(0x7F, PM_DATA);
pci_write_config32(dev, EHCI_BAR_INDEX, base); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER); } diff --git a/src/soc/amd/stoneyridge/fadt.c b/src/soc/amd/stoneyridge/fadt.c index 9e5a795..fb3410c 100644 --- a/src/soc/amd/stoneyridge/fadt.c +++ b/src/soc/amd/stoneyridge/fadt.c @@ -39,7 +39,7 @@ * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. */ -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header);
@@ -125,7 +125,7 @@ fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrl = SYS_RESET; fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6; @@ -169,8 +169,8 @@ fadt->x_pm1b_cnt_blk.addrh = 0x0;
/* - * Note: Under this current AMD C state implementation, this is no longer - * used and should not be reported to OS. + * Note: Under this current AMD C state implementation, this is no + * longer used and should not be reported to OS. */ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 0; diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c index a0935e7..d3f5f6c 100644 --- a/src/soc/amd/stoneyridge/fixme.c +++ b/src/soc/amd/stoneyridge/fixme.c @@ -14,6 +14,7 @@ */
#include <cpu/x86/mtrr.h> +#include <soc/pci_devs.h> #include <agesawrapper.h> #include <amdlib.h>
@@ -25,7 +26,7 @@ AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xf4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@@ -35,29 +36,29 @@ */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; + PciData = 0x00fedf00; PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; + PciData = (0xfed00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8c); + PciData = 0x00fecf00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc4); + PciData = 0x0000f000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -73,25 +74,25 @@ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ - (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | + (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) + | 1; + LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
/* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); + PciData = 0xff03ffd5; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, PCU_DEV, LPC_FUNC, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ - 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20d, &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { + LibAmdMsrRead(0x1b, &MsrReg, &StdHeader); MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x1b, &MsrReg, &StdHeader); } } diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index dcef11d..d49637a 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -22,7 +22,7 @@ { uint32_t reg;
- reg = read32((void*)(uintptr_t)gpio_num); + reg = read32((void *)(uintptr_t)gpio_num);
return !!(reg & GPIO_PIN_STS); } diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/hudson.c index 8307014..e75a809 100644 --- a/src/soc/amd/stoneyridge/hudson.c +++ b/src/soc/amd/stoneyridge/hudson.c @@ -65,16 +65,16 @@ case (0x14 << 3) | 7: /* 0:14.7 SD */ if (dev->enabled == 0) { // read the VENDEV ID - device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); - u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16; + device_t sd_dev = dev_find_slot(0, PCI_DEVFN(0x14, 7)); + u32 sd_device_id = pci_read_config32(sd_dev, 0) >> 16; /* turn off the SDHC controller in the PM reg */ u8 reg8; if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) { reg8 = pm_read8(PM_HUD_SD_FLASH_CTRL); reg8 &= ~BIT(0); pm_write8(PM_HUD_SD_FLASH_CTRL, reg8); - } - else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) { + } else if (sd_device_id + == PCI_DEVICE_ID_AMD_YANGTZE_SD) { reg8 = pm_read8(PM_YANG_SD_FLASH_CTRL); reg8 &= ~BIT(0); pm_write8(PM_YANG_SD_FLASH_CTRL, reg8); diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c index b4e1d9d..7e40a99 100644 --- a/src/soc/amd/stoneyridge/imc.c +++ b/src/soc/amd/stoneyridge/imc.c @@ -45,13 +45,12 @@ write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff);
- reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); - reg8 &= 0x8F; + reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4); + reg8 &= 0x8f; reg8 |= 0x10; - pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8); + pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4, reg8); }
-#ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { AMD_CONFIG_PARAMS StdHeader; @@ -62,12 +61,12 @@ regs[0] = 0; regs[1] = 0; FunNum = Fun_80; - for (i = 0; i <= 1; i++) + for (i = 0 ; i <= 1 ; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); WaitForEcLDN9MailboxCmdAck(&StdHeader);
- for (i = 2; i <= 9; i++) + for (i = 2 ; i <= 9 ; i++) ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader);
/* enable thermal zone 0 */ @@ -75,14 +74,13 @@ regs[0] = 0; regs[1] = 0; FunNum = Fun_81; - for (i = 0; i <= 9; i++) + for (i = 0 ; i <= 9 ; i++) WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); WaitForEcLDN9MailboxCmdAck(&StdHeader); } -#endif
-/* Bettong Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: * HWM will fail to read the input temperature via I2C if other * software switches the I2C address. AMD recommends using IMC @@ -94,8 +92,13 @@ imc_reg_init();
FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
- LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + /* 1 IMC, 0 HWM */ + FchParams->Hwm.HwmControl = 1; + + /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ + FchParams->Imc.ImcEnableOverWrite = 1; + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), + FchParams->StdHeader); } diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h index 361c06f..f3f60d3 100644 --- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h @@ -22,7 +22,7 @@ * routing table */
-#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_A 0x00 /* INT A */ #define PIRQ_B 0x01 /* INT B */ #define PIRQ_C 0x02 /* INT C */ @@ -33,12 +33,12 @@ #define PIRQ_H 0x07 /* INT H */ #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ -#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ -#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ +#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -46,7 +46,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SD 0x17 /* SD */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h index 30ab0d4..ab1f70b 100644 --- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h +++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h @@ -16,17 +16,22 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-const char * intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x7F] = "RSVD\t", +const char *intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", + "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", + "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", + "PerMon\t", "SD\t\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", + "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", + "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x7f] = "RSVD\t", [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", [0x62] = "GPIO\t", - [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t", + [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t", };
#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 07d4009..a66701a 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -30,98 +30,98 @@ #define GPIO_0 (GPIO_BANK0_CONTROL + 0x00) #define GPIO_1 (GPIO_BANK0_CONTROL + 0x04) #define GPIO_2 (GPIO_BANK0_CONTROL + 0x08) -#define GPIO_3 (GPIO_BANK0_CONTROL + 0x0C) +#define GPIO_3 (GPIO_BANK0_CONTROL + 0x0c) #define GPIO_4 (GPIO_BANK0_CONTROL + 0x10) #define GPIO_5 (GPIO_BANK0_CONTROL + 0x14) #define GPIO_6 (GPIO_BANK0_CONTROL + 0x18) -#define GPIO_7 (GPIO_BANK0_CONTROL + 0x1C) +#define GPIO_7 (GPIO_BANK0_CONTROL + 0x1c) #define GPIO_8 (GPIO_BANK0_CONTROL + 0x20) #define GPIO_9 (GPIO_BANK0_CONTROL + 0x24) #define GPIO_10 (GPIO_BANK0_CONTROL + 0x28) -#define GPIO_11 (GPIO_BANK0_CONTROL + 0x2C) +#define GPIO_11 (GPIO_BANK0_CONTROL + 0x2c) #define GPIO_12 (GPIO_BANK0_CONTROL + 0x30) #define GPIO_13 (GPIO_BANK0_CONTROL + 0x34) #define GPIO_14 (GPIO_BANK0_CONTROL + 0x38) -#define GPIO_15 (GPIO_BANK0_CONTROL + 0x3C) +#define GPIO_15 (GPIO_BANK0_CONTROL + 0x3c) #define GPIO_16 (GPIO_BANK0_CONTROL + 0x40) #define GPIO_17 (GPIO_BANK0_CONTROL + 0x44) #define GPIO_18 (GPIO_BANK0_CONTROL + 0x48) -#define GPIO_19 (GPIO_BANK0_CONTROL + 0x4C) +#define GPIO_19 (GPIO_BANK0_CONTROL + 0x4c) #define GPIO_20 (GPIO_BANK0_CONTROL + 0x50) #define GPIO_21 (GPIO_BANK0_CONTROL + 0x54) #define GPIO_22 (GPIO_BANK0_CONTROL + 0x58) -#define GPIO_23 (GPIO_BANK0_CONTROL + 0x5C) +#define GPIO_23 (GPIO_BANK0_CONTROL + 0x5c) #define GPIO_24 (GPIO_BANK0_CONTROL + 0x60) #define GPIO_25 (GPIO_BANK0_CONTROL + 0x64) #define GPIO_26 (GPIO_BANK0_CONTROL + 0x68) -#define GPIO_39 (GPIO_BANK0_CONTROL + 0x9C) -#define GPIO_42 (GPIO_BANK0_CONTROL + 0xA8) +#define GPIO_39 (GPIO_BANK0_CONTROL + 0x9c) +#define GPIO_42 (GPIO_BANK0_CONTROL + 0xa8)
/* GPIO_64 - GPIO_127 */ #define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600) #define GPIO_64 (GPIO_BANK1_CONTROL + 0x00) #define GPIO_65 (GPIO_BANK1_CONTROL + 0x04) #define GPIO_66 (GPIO_BANK1_CONTROL + 0x08) -#define GPIO_67 (GPIO_BANK1_CONTROL + 0x0C) +#define GPIO_67 (GPIO_BANK1_CONTROL + 0x0c) #define GPIO_68 (GPIO_BANK1_CONTROL + 0x10) #define GPIO_69 (GPIO_BANK1_CONTROL + 0x14) #define GPIO_70 (GPIO_BANK1_CONTROL + 0x18) -#define GPIO_71 (GPIO_BANK1_CONTROL + 0x1C) +#define GPIO_71 (GPIO_BANK1_CONTROL + 0x1c) #define GPIO_72 (GPIO_BANK1_CONTROL + 0x20) #define GPIO_74 (GPIO_BANK1_CONTROL + 0x28) -#define GPIO_75 (GPIO_BANK1_CONTROL + 0x2C) +#define GPIO_75 (GPIO_BANK1_CONTROL + 0x2c) #define GPIO_76 (GPIO_BANK1_CONTROL + 0x30) #define GPIO_84 (GPIO_BANK1_CONTROL + 0x50) #define GPIO_85 (GPIO_BANK1_CONTROL + 0x54) #define GPIO_86 (GPIO_BANK1_CONTROL + 0x58) -#define GPIO_87 (GPIO_BANK1_CONTROL + 0x5C) +#define GPIO_87 (GPIO_BANK1_CONTROL + 0x5c) #define GPIO_88 (GPIO_BANK1_CONTROL + 0x60) #define GPIO_89 (GPIO_BANK1_CONTROL + 0x64) #define GPIO_90 (GPIO_BANK1_CONTROL + 0x68) -#define GPIO_91 (GPIO_BANK1_CONTROL + 0x6C) +#define GPIO_91 (GPIO_BANK1_CONTROL + 0x6c) #define GPIO_92 (GPIO_BANK1_CONTROL + 0x70) #define GPIO_93 (GPIO_BANK1_CONTROL + 0x74) -#define GPIO_95 (GPIO_BANK1_CONTROL + 0x7C) +#define GPIO_95 (GPIO_BANK1_CONTROL + 0x7c) #define GPIO_96 (GPIO_BANK1_CONTROL + 0x80) #define GPIO_97 (GPIO_BANK1_CONTROL + 0x84) #define GPIO_98 (GPIO_BANK1_CONTROL + 0x88) -#define GPIO_99 (GPIO_BANK1_CONTROL + 0x8C) +#define GPIO_99 (GPIO_BANK1_CONTROL + 0x8c) #define GPIO_100 (GPIO_BANK1_CONTROL + 0x90) #define GPIO_101 (GPIO_BANK1_CONTROL + 0x94) #define GPIO_102 (GPIO_BANK1_CONTROL + 0x98) -#define GPIO_113 (GPIO_BANK1_CONTROL + 0xC4) -#define GPIO_114 (GPIO_BANK1_CONTROL + 0xC8) -#define GPIO_115 (GPIO_BANK1_CONTROL + 0xCC) -#define GPIO_116 (GPIO_BANK1_CONTROL + 0xD0) -#define GPIO_117 (GPIO_BANK1_CONTROL + 0xD4) -#define GPIO_118 (GPIO_BANK1_CONTROL + 0xD8) -#define GPIO_119 (GPIO_BANK1_CONTROL + 0xDC) -#define GPIO_120 (GPIO_BANK1_CONTROL + 0xE0) -#define GPIO_121 (GPIO_BANK1_CONTROL + 0xE4) -#define GPIO_122 (GPIO_BANK1_CONTROL + 0xE8) -#define GPIO_126 (GPIO_BANK1_CONTROL + 0xF8) +#define GPIO_113 (GPIO_BANK1_CONTROL + 0xc4) +#define GPIO_114 (GPIO_BANK1_CONTROL + 0xc8) +#define GPIO_115 (GPIO_BANK1_CONTROL + 0xcc) +#define GPIO_116 (GPIO_BANK1_CONTROL + 0xd0) +#define GPIO_117 (GPIO_BANK1_CONTROL + 0xd4) +#define GPIO_118 (GPIO_BANK1_CONTROL + 0xd8) +#define GPIO_119 (GPIO_BANK1_CONTROL + 0xdc) +#define GPIO_120 (GPIO_BANK1_CONTROL + 0xe0) +#define GPIO_121 (GPIO_BANK1_CONTROL + 0xe4) +#define GPIO_122 (GPIO_BANK1_CONTROL + 0xe8) +#define GPIO_126 (GPIO_BANK1_CONTROL + 0xf8)
/* GPIO_128 - GPIO_183 */ #define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700) #define GPIO_129 (GPIO_BANK2_CONTROL + 0x04) #define GPIO_130 (GPIO_BANK2_CONTROL + 0x08) -#define GPIO_131 (GPIO_BANK2_CONTROL + 0x0C) +#define GPIO_131 (GPIO_BANK2_CONTROL + 0x0c) #define GPIO_132 (GPIO_BANK2_CONTROL + 0x10) #define GPIO_133 (GPIO_BANK2_CONTROL + 0x14) #define GPIO_134 (GPIO_BANK2_CONTROL + 0x18) -#define GPIO_135 (GPIO_BANK2_CONTROL + 0x1C) +#define GPIO_135 (GPIO_BANK2_CONTROL + 0x1c) #define GPIO_136 (GPIO_BANK2_CONTROL + 0x20) #define GPIO_137 (GPIO_BANK2_CONTROL + 0x24) #define GPIO_138 (GPIO_BANK2_CONTROL + 0x28) -#define GPIO_139 (GPIO_BANK2_CONTROL + 0x2C) +#define GPIO_139 (GPIO_BANK2_CONTROL + 0x2c) #define GPIO_140 (GPIO_BANK2_CONTROL + 0x30) #define GPIO_141 (GPIO_BANK2_CONTROL + 0x34) #define GPIO_142 (GPIO_BANK2_CONTROL + 0x38) -#define GPIO_143 (GPIO_BANK2_CONTROL + 0x3C) +#define GPIO_143 (GPIO_BANK2_CONTROL + 0x3c) #define GPIO_144 (GPIO_BANK2_CONTROL + 0x40) #define GPIO_145 (GPIO_BANK2_CONTROL + 0x44) #define GPIO_146 (GPIO_BANK2_CONTROL + 0x48) -#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4C) +#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4c) #define GPIO_148 (GPIO_BANK2_CONTROL + 0x50)
typedef uint32_t gpio_t; diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h index bfe506e..c69ab67 100644 --- a/src/soc/amd/stoneyridge/include/soc/hudson.h +++ b/src/soc/amd/stoneyridge/include/soc/hudson.h @@ -29,6 +29,9 @@ */ #define PM_MMIO_BASE 0xfed80300
+#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 @@ -44,15 +47,17 @@ #define PM_TMR_BLK 0x64 #define PM_CPU_CTRL 0x66 #define PM_GPE0_BLK 0x68 -#define PM_ACPI_SMI_CMD 0x6A +#define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 -#define PM_PMIO_DEBUG 0xD2 -#define PM_MANUAL_RESET 0xD3 -#define PM_HUD_SD_FLASH_CTRL 0xE7 -#define PM_YANG_SD_FLASH_CTRL 0xE8 -#define PM_PCIB_CFG 0xEA +#define PM_PMIO_DEBUG 0xd2 +#define PM_MANUAL_RESET 0xd3 +#define PM_HUD_SD_FLASH_CTRL 0xe7 +#define PM_YANG_SD_FLASH_CTRL 0xe8 +#define PM_PCIB_CFG 0xea
-#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define SYS_RESET 0xcf9 + +#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE #define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ @@ -69,10 +74,10 @@ #define REV_STONEYRIDGE_A11 0x11 #define REV_STONEYRIDGE_A12 0x12
-#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xFEC10000 +#define SPI_BASE_ADDRESS 0xfec10000
#define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) @@ -122,7 +127,7 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
-#define SPI_CNTRL0 0x00 +#define SPI_CNTRL0 0x00 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) /* Nominal is 16.7MHz on older devices, 33MHz on newer */ #define SPI_READ_MODE_NOM 0x00000000 @@ -138,7 +143,7 @@
#define SPI_CNTRL1 0x0c /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8
@@ -154,22 +159,24 @@ #define SPI_SPEED_800K (BIT(2) | BIT(0)) #define SPI_NORM_SPEED_NEW_SH 12 #define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_ALT_SPEED_NEW_SH 4 #define SPI_TPM_SPEED_NEW_SH 0
-#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15)
static inline int hudson_sata_enable(void) { /* True if IDE or AHCI. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 2); + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 2); }
static inline int hudson_ide_enable(void) { /* True if IDE or LEGACY IDE. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 3); }
void configure_hudson_uart(void); diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index cfd79d8..f044542 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -22,12 +22,12 @@ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 #define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
#define XHCI2_DEV 0x10 #define XHCI2_FUNC 1 #define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
/* SATA */ #define SATA_DEV 0x11 @@ -35,7 +35,7 @@ #define SATA_IDE_DEVID 0x7800 #define AHCI_DEVID_MS 0x7801 #define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
/* OHCI */ #define OHCI1_DEV 0x12 @@ -47,10 +47,10 @@ #define OHCI4_DEV 0x14 #define OHCI4_FUNC 5 #define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
/* EHCI */ #define EHCI1_DEV 0x12 @@ -60,47 +60,47 @@ #define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 #define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
/* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEVID 0x780b +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
/* IDE */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) #define IDE_DEV 0x14 #define IDE_FUNC 1 -#define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEVID 0x780c +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif
/* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 -#define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEVID 0x780d +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
/* LPC BUS */ #define PCU_DEV 0x14 #define LPC_FUNC 3 -#define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define LPC_DEVID 0x780e +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC)
/* PCI Ports */ #define SB_PCI_PORT_DEV 0x14 #define SB_PCI_PORT_FUNC 4 -#define SB_PCI_PORT_DEVID 0x780F -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEVID 0x780f +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
/* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 #define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
/* PCIe Ports */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) @@ -113,10 +113,10 @@ #define SB_PCIE_PORT2_DEVID 0x7821 #define SB_PCIE_PORT3_DEVID 0x7822 #define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif
#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index d4499fc..c9b19e5 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -38,7 +38,7 @@ #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 +#define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally @@ -65,6 +65,6 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
#endif /* STONEYRIDGE_SMBUS_H */ diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index b2ee843..64a4e65 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -28,6 +28,7 @@ #include <arch/acpi.h> #include <pc80/i8254.h> #include <pc80/i8259.h> +#include <soc/pci_devs.h> #include <soc/hudson.h> #include <vboot/vbnv.h>
@@ -38,7 +39,7 @@ device_t sm_dev;
/* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); @@ -59,16 +60,21 @@ /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can - interrupt and visit LPC. */ + /* Keep the old way. i.e., when bus master/DMA cycle is going + * on on LPC, it holds PCI grant, so no LPC slave cycle can + * interrupt and visit LPC. + */ + byte &= ~(1 << 0); pci_write_config8(dev, 0x78, byte);
- /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ - /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ - byte = pci_read_config8(dev, 0xBB); + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads + * code from SPI ROM + * bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. + * todo: verify both these against BKDG + */ + byte = pci_read_config8(dev, 0xbb); byte |= 1 << 0 | 1 << 3; - pci_write_config8(dev, 0xBB, byte); + pci_write_config8(dev, 0xbb, byte);
cmos_check_update_date();
@@ -83,10 +89,10 @@ cmos_init(0);
/* Initialize i8259 pic */ - setup_i8259 (); + setup_i8259();
/* Initialize i8254 timers */ - setup_i8254 (); + setup_i8254();
/* Set up SERIRQ, enable continuous mode */ byte = (BIT(4) | BIT(7)); @@ -101,7 +107,7 @@ struct resource *res;
/* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -114,10 +120,11 @@ res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, + IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; @@ -135,8 +142,9 @@ /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); - spi_enable_bits &= 0xF; - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); + spi_enable_bits &= 0xf; + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, + res->base | spi_enable_bits);
pci_dev_set_resources(dev); } @@ -153,25 +161,26 @@ u32 reg, reg_x; int var_num = 0; u16 reg_var[3]; - u16 reg_size[1] = {512}; + u16 reg_size[1] = {512}; u8 wiosize = pci_read_config8(dev, 0x74);
- /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, - * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes - * it must be 512 bytes to be able to allocate the fresh LPC window. + /* Be bit relaxed, tolerate that LPC region might be bigger than + * resource we try to fit, do it like this for all regions < 16 bytes. + * If there is a resource > 16 bytes it must be 512 bytes to be able + * to allocate the fresh LPC window. * - * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, - * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size - * The code tries to check if resource can fit into this region + * AGESA likes to enable already one LPC region in wide port base + * 0x64-0x65, using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size + * The code tries to check if resource can fit into this region. */
reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48);
- /* check if ranges are free and not use them if entry is just already taken */ + /* check if ranges are free and don't use them if already taken */ if (reg_x & (1 << 2)) var_num = 1; - /* just in case check if someone did not manually set other ranges too */ + /* just in case check if someone did not manually set other ranges */ if (reg_x & (1 << 24)) var_num = 2;
@@ -186,14 +195,15 @@ reg_var[1] = pci_read_config16(dev, 0x66); reg_var[0] = pci_read_config16(dev, 0x64);
- for (link = dev->link_list; link; link = link->next) { + /* todo: clean up the code style here */ + for (link = dev->link_list ; link ; link = link->next) { device_t child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; - for (res = child->resource_list; res; res = res->next) { + for (res = child->resource_list ; res ; res = res->next) { u32 base, end; /* don't need long long */ u32 rsize, set = 0, set_x = 0; if (!(res->flags & IORESOURCE_IO)) @@ -238,7 +248,7 @@ set |= (1 << 10); rsize = 8; break; - case 0x300: /* 0x300 -0x301 */ + case 0x300: /* 0x300 - 0x301 */ set |= (1 << 18); rsize = 2; break; @@ -269,7 +279,7 @@ default: rsize = 0; /* try AGESA allocated region in region 0 */ - if ((var_num > 0) && ((base >=reg_var[0]) && + if ((var_num > 0) && ((base >= reg_var[0]) && ((base + res->size) <= (reg_var[0] + reg_size[0])))) rsize = reg_size[0]; } diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index 02e5b79..cad06bf 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -43,8 +43,8 @@ Bar3Addr = PspLibPciReadPspConfig(0x20); Tmp64 = Bar3Addr; printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); + LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); + LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); }
static void model_15_init(device_t dev) @@ -67,11 +67,11 @@
// BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; - wrmsr(0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); - for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); + for (msrno = MTRR_FIX_4K_C0000 ; msrno <= MTRR_FIX_4K_F8000 ; msrno++) wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); @@ -85,7 +85,7 @@ /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0 ; i < 6 ; i++) wrmsr(MCI_STATUS + (i * 4), msr);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 074bb0a..050709b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -53,31 +53,38 @@ #endif
typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 + u32 base; /* [47:27] at [28:8] */ + u32 mask; /* [47:27] at [28:8] and enable at bit 0 */ } dram_base_mask_t;
-static unsigned node_nums; -static unsigned sblink; +static unsigned int node_nums; +static unsigned int sblink; static device_t __f0_dev; static device_t __f1_dev; static device_t __f2_dev; static device_t __f4_dev; -static unsigned fx_dev = 0; +static unsigned int fx_dev = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { device_t dev = __f1_dev; dram_base_mask_t d; u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + + /* [39:24] at [31:16] */ + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); + + /* mask out DramMask [26:24] too */ + d.mask = ((temp & 0xfff80000) >> (8 + 3)); + + /* [47:40] at [7:0] */ + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); + d.mask |= (temp & 1); /* enable bit */ + d.base = ((temp & 0xfff80000) >> (8 + 3)); + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; d.base |= temp << 21; return d; } @@ -86,18 +93,20 @@ u32 io_min, u32 io_max) { u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit + /* io range allocation. Limit */ + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) + | ((io_max & 0xf0) << (12 - 4)); pci_write_config32(__f1_dev, reg + 4, tempreg); - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? + tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ pci_write_config32(__f1_dev, reg, tempreg); }
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) { u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); //limit + /* io range allocation. Limit */ + tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); pci_write_config32(__f1_dev, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); pci_write_config32(__f1_dev, reg, tempreg); @@ -120,14 +129,14 @@ die("Cannot find 0:0x18.[0|1]\n"); }
-static u32 f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned int reg) { if (fx_dev == 0) get_fx_dev(); return pci_read_config32(__f1_dev, reg); }
-static void f1_write_config32(unsigned reg, u32 value) +static void f1_write_config32(unsigned int reg, u32 value) { if (fx_dev == 0) get_fx_dev(); @@ -148,7 +157,6 @@
static void read_resources(device_t dev) { - /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in @@ -160,7 +168,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50];
/* Make certain the resource has actually been set */ @@ -186,15 +194,15 @@ rend = resource_end(resource);
/* Get the register and link */ - reg = resource->index & 0xfff; // 4k + reg = resource->index & 0xfff; /* 4k */ link_num = IOINDEX_LINK(resource->index);
- if (resource->flags & IORESOURCE_IO) { + if (resource->flags & IORESOURCE_IO) set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24), rbase >> 8, rend >> 8); // [39:8] - } + else if (resource->flags & IORESOURCE_MEM) + set_mmio_addr_reg(nodeid, link_num, reg, + (resource->index >> 24), rbase >> 8, rend >> 8); + resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num); @@ -212,16 +220,16 @@
/* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { + for (link = dev->link_list ; link ; link = link->next) if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) break; - }
/* no VGA card installed */ if (link == NULL) return;
- printk(BIOS_DEBUG, "VGA: %s link %d has VGA device\n", dev_path(dev), sblink); + printk(BIOS_DEBUG, "VGA: %s link %d has VGA device\n", + dev_path(dev), sblink); set_vga_enable_reg(0, sblink); }
@@ -235,15 +243,12 @@ create_vga_resource(dev);
/* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { + for (res = dev->resource_list ; res ; res = res->next) set_resource(dev, res, 0); - }
- for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { + for (bus = dev->link_list ; bus ; bus = bus->next) + if (bus->children) assign_resources(bus); - } - } }
static void northbridge_init(struct device *dev) @@ -259,11 +264,13 @@
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
return (unsigned long)current; } @@ -312,7 +319,7 @@ ivrs = agesawrapper_getlateinitptr(PICK_IVRS); if (ivrs != NULL) { memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; + ivrs = (acpi_header_t *)current; current += ivrs->length; acpi_add_table(rsdp, ivrs); } else { @@ -322,10 +329,10 @@ /* SRAT */ current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); if (srat != NULL) { memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; + srat = (acpi_srat_t *)current; current += srat->header.length; acpi_add_table(rsdp, srat); } else { @@ -335,10 +342,10 @@ /* SLIT */ current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); if (slit != NULL) { memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; + slit = (acpi_slit_t *)current; current += slit->header.length; acpi_add_table(rsdp, slit); } else { @@ -348,31 +355,28 @@ /* ALIB */ current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *) current; + alib = (acpi_header_t *)current; current += alib->length; acpi_add_table(rsdp, (void *)alib); - } - else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." + " Skipping.\n"); }
- /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ - /* SSDT */ current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); if (ssdt != NULL) { memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; + ssdt = (acpi_header_t *)current; current += ssdt->length; - } - else { + } else { printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); + acpi_add_table(rsdp, ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); return current; @@ -400,8 +404,8 @@ device_t dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + pci_write_config32(dev, 0xf8, 0); + pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */ dev = dev_find_slot(0, PCI_DEVFN(1, 1)); @@ -412,32 +416,33 @@
void domain_read_resources(device_t dev) { - unsigned reg; + unsigned int reg;
/* Find the already assigned resource pairs */ get_fx_dev(); - for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) { u32 base, limit; base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned nodeid, reg_link; + unsigned int nodeid, reg_link; device_t reg_dev; - if (reg < 0xc0) { // mmio + if (reg < 0xc0) /* mmio */ nodeid = (limit & 0xf) + (base & 0x30); - } else { // io + else /* io */ nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } + reg_link = (limit >> 4) & 7; reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { + res = new_resource(reg_dev, + IOINDEX(0x1000 + reg, + reg_link)); + if (res) res->flags = 1; - } } } } @@ -461,7 +466,7 @@
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { - unsigned hole_startk; + unsigned int hole_startk; int node_id; };
@@ -477,7 +482,7 @@ if (hole & 2) { /* We found the hole */ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; - mem_hole.node_id = 0; // record the node # with hole + mem_hole.node_id = 0; /* record the node # with hole */ }
return mem_hole; @@ -503,25 +508,29 @@ * >= 2G 256M * < 2G 128M */ - sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocate for C6 when finding UMA size + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); - printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", - __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); + printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size" + " %lluMB, topmem size %lluMB\n", __func__, + (unsigned long)sysmem_gb, + topmem2 >> ONE_MB_SHIFT, + topmem >> ONE_MB_SHIFT);
- if (sysmem_gb >= 6) { + if (sysmem_gb >= 6) uma_memory_size = 1024 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 4) { + else if (sysmem_gb >= 4) uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 2) { + else if (sysmem_gb >= 2) uma_memory_size = 256 << ONE_MB_SHIFT; - } else { + else uma_memory_size = 128 << ONE_MB_SHIFT; - } + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
- printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start" + " 0x%08llx\n", __func__, uma_memory_size, + uma_memory_base); } }
@@ -538,13 +547,12 @@ #endif
pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { + for (link = dev->link_list ; link ; link = link->next) pci_tolm = find_pci_tolm(link); - }
mmio_basek = pci_tolm >> 10; /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); + mmio_basek &= ~((1 << 6) - 1);
/* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M * MMIO hole. If you fix this here, please fix amdk8, too. @@ -553,15 +561,15 @@ mmio_basek &= ~((64 * 1024) - 1);
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek + /* if the hw mem hole is already set in raminit stage, here we will + * compare mmio_basek and hole_basek. if mmio_basek is bigger that + * hole_basek and will use hole_basek as mmio_basek and we don't need + * to reset hole. Otherwise we reset the hole to the mmio_basek */
mem_hole = get_hw_mem_hole_info();
- /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ + /* Use hole_basek as mmio_basek, and no need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; reset_memhole = 0; @@ -569,22 +577,26 @@ #endif
idx = 0x10; - for (i = 0; i < node_nums; i++) { + for (i = 0 ; i < node_nums ; i++) { dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T + resource_t basek, limitk, sizek; /* 4 1T */
d = get_dram_base_mask(i);
if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + /* could overflow, we may lose 6 bit here */ + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; + limitk = ((resource_t)(((d.mask & ~1) + 0x000ff) + & 0x1fffff00)) << 9;
sizek = limitk - basek;
/* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) + (16 * 16)))) { - ram_resource(dev, (idx | i), basek, ((8 * 64) + (8 * 16)) - basek); + if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) + + (16 * 16)))) { + ram_resource(dev, (idx | i), basek, + ((8 * 64) + (8 * 16)) - basek); idx += 0x10; basek = (8 * 64) + (16 * 16); sizek = limitk - ((8 * 64) + (16 * 16)); @@ -592,12 +604,13 @@ }
/* split the region to accommodate pci memory space */ - if ((basek < 4 * 1024 * 1024 ) && (limitk > mmio_basek)) { + if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { - unsigned pre_sizek; + unsigned int pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { - ram_resource(dev, (idx | i), basek, pre_sizek); + if (pre_sizek > 0) { + ram_resource(dev, (idx | i), basek, + pre_sizek); idx += 0x10; sizek -= pre_sizek; if (!ramtop) @@ -607,8 +620,7 @@ } if ((basek + sizek) <= 4 * 1024 * 1024) { sizek = 0; - } - else { + } else { uint64_t topmem2 = bsp_topmem2(); basek = 4 * 1024 * 1024; sizek = topmem2 / 1024 - basek; @@ -617,24 +629,25 @@
ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; - printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx," + " limitk=%08llx\n", i, mmio_basek, basek, + limitk); if (!ramtop) ramtop = mmio_basek * 1024; }
if (IS_ENABLED(CONFIG_GFXUMA)) { set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); + uma_resource(dev, 7, uma_memory_base >> 10, + uma_memory_size >> 10); } else { set_top_of_ram(ramtop); }
- for (link = dev->link_list; link; link = link->next) { - if (link->children) { + for (link = dev->link_list ; link ; link = link->next) + if (link->children) assign_resources(link); - } - } + /* * Reserve everything between A segment and 1MB: * @@ -645,12 +658,14 @@ reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); }
-static void sysconf_init(device_t dev) // first node +/* first node */ +static void sysconf_init(device_t dev) { - sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; // NodeCnt[2:0] + /* don't forget sublink1 */ + sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; + /* NodeCnt[2:0] */ + node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; } -
void cpu_bus_scan(device_t dev) { @@ -671,26 +686,29 @@
dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, + CONFIG_CDB); die(""); } sysconf_init(dev_mc); /* sets global node_nums */
if (node_nums != 1) - die("node_nums != 1. This is an SOC. Something is terribly wrong."); + die("node_nums != 1. This is an SOC." + " Something is terribly wrong.");
/* Get max and actual number of cores */ pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT); - core_max = 1 << ((pccount >> 12) & 0xF); + core_max = 1 << ((pccount >> 12) & 0xf); core_nums = (pccount & 0xF);
- family = (cpuid_eax(1) >> 20) & 0xFF; + family = (cpuid_eax(1) >> 20) & 0xff;
cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); - siblings = pci_read_config32(cdb_dev, 0x84) & 0xFF; + siblings = pci_read_config32(cdb_dev, 0x84) & 0xff;
- printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d, siblings=%d\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d," + " siblings=%d\n", dev_path(cdb_dev), 0x0f + family, + core_max, core_nums, siblings);
/* * APIC ID calucation is tightly coupled with AGESA v5 code. @@ -717,10 +735,11 @@ enable_node = cdb_dev && cdb_dev->enabled; cpu_bus = dev->link_list;
- for (j = 0; j <= siblings; j++ ) { + for (j = 0 ; j <= siblings ; j++) { apic_id = lapicid_start + j; - printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n", - lapicid_start, node_nums, j, apic_id); + printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x," + " apicid=0x%x\n", lapicid_start, node_nums, + j, apic_id);
cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) @@ -739,10 +758,12 @@ { u32 new_vendev; new_vendev = - ((0x100298E0 <= vendev) && (vendev <= 0x100298EF)) ? 0x100298E0 : vendev; + ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? + 0x100298e0 : vendev;
if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", + vendev, new_vendev);
return new_vendev; } diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index beaf281..63f5c2a 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -18,8 +18,9 @@
#include <arch/io.h> #include <reset.h> +#include <soc/hudson.h>
-#define HT_INIT_CONTROL 0x6C +#define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1 << 5)
@@ -40,6 +41,6 @@ * --- it only reset coherent link table, * but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (0 << 2) | (1 << 1), SYS_RESET); + outb((0 << 3) | (1 << 2) | (1 << 1), SYS_RESET); } diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 32090d2..bd013c8 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -32,11 +32,11 @@ #define AHCI_BASE_ADDRESS_REG 0x24 #define MISC_CONTROL_REG 0x40 #define UNLOCK_BIT (1<<0) - #define SATA_CAPABILITIES_REG 0xFC + #define SATA_CAPABILITIES_REG 0xfc #define CFG_CAP_SPM (1<<12)
- volatile u32 *ahci_ptr = - (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + volatile u32 *ahci_ptr = (u32 *)(pci_read_config32(dev, + AHCI_BASE_ADDRESS_REG) & 0xffffff00); u32 temp;
/* unlock the write-protect */ @@ -45,7 +45,8 @@ pci_write_config32(dev, MISC_CONTROL_REG, temp);
/* set the SATA AHCI mode to allow port expanders */ - *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) + |= CFG_CAP_SPM;
/* lock the write-protect */ temp = pci_read_config32(dev, MISC_CONTROL_REG); diff --git a/src/soc/amd/stoneyridge/sd.c b/src/soc/amd/stoneyridge/sd.c index 484dee4..7188aad 100644 --- a/src/soc/amd/stoneyridge/sd.c +++ b/src/soc/amd/stoneyridge/sd.c @@ -25,27 +25,26 @@ { u32 stepping;
- stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), + 0xfc);
struct soc_amd_stoneyridge_config *sd_chip = (struct soc_amd_stoneyridge_config *)(dev->chip_info);
if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ - pci_write_config32(dev, 0xA4, 0x31FEC8B2); - pci_write_config32(dev, 0xA8, 0x00002503); - pci_write_config32(dev, 0xB0, 0x02180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); - } - else { /* SD 2.0 mode */ - if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ - pci_write_config32(dev, 0xA4, 0x31DE32B2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000058B); - } - else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); + pci_write_config32(dev, 0xa4, 0x31fec8b2); + pci_write_config32(dev, 0xa8, 0x00002503); + pci_write_config32(dev, 0xb0, 0x02180c19); + pci_write_config32(dev, 0xd0, 0x0000078b); + } else { /* SD 2.0 mode */ + if ((stepping & 0x0000000f) == 0) { /* Stepping A0 */ + pci_write_config32(dev, 0xa4, 0x31de32b2); + pci_write_config32(dev, 0xb0, 0x01180c19); + pci_write_config32(dev, 0xd0, 0x0000058b); + } else { /* Stepping >= A1 */ + pci_write_config32(dev, 0xa4, 0x31fe3fb2); + pci_write_config32(dev, 0xb0, 0x01180c19); + pci_write_config32(dev, 0xd0, 0x0000078b); } } } diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index e890c47..37565dd 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -45,11 +45,10 @@
val = inb(smbus_io_base + SMBHSTSTAT); val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { + if (val & 0x1c) return -5; /* error */ - } if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + outb(val, smbus_io_base + SMBHSTSTAT); /* clear sts */ return 0; } } while (--loops); @@ -60,22 +59,20 @@ { u8 byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - }
/* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start the command */ outb(byte, smbus_io_base + SMBHSTCTRL);
/* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - }
/* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD); @@ -87,9 +84,8 @@ { u8 byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - }
/* set the command... */ outb(val, smbus_io_base + SMBHSTCMD); @@ -99,13 +95,12 @@
byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL);
/* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - }
return 0; } @@ -115,9 +110,8 @@ { u8 byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - }
/* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -127,13 +121,12 @@
byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL);
/* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - }
/* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0); @@ -146,9 +139,8 @@ { u8 byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) return -2; /* not ready */ - }
/* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -161,13 +153,12 @@
byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */ outb(byte, smbus_io_base + SMBHSTCTRL);
/* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) return -3; /* timeout or error */ - }
return 0; } @@ -188,8 +179,11 @@ tmp &= ~mask; tmp |= val;
- /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); } @@ -210,8 +204,11 @@ tmp &= ~mask; tmp |= val;
- //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); } @@ -219,8 +216,7 @@ /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, - u32 mask, u32 val) +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp;
diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 863631a..73e6702 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -20,39 +20,42 @@ #include <Porting.h> #include <AGESA.h> #include <amdlib.h> +#include <soc/hudson.h> #include <dimmSpd.h>
/*----------------------------------------------------------------------------- * * readSmbusByteData - read a single SPD byte from any offset */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +static int readSmbusByteData(int iobase, int address, char *buffer, int offset) { unsigned int status; UINT64 limit;
address |= 1; // set read bit
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command + __outbyte(iobase + 0, 0xff); // clear error status + __outbyte(iobase + 1, 0x1f); // clear error status + __outbyte(iobase + 3, offset); // offset in eeprom + __outbyte(iobase + 4, address); // slave address and read bit + __outbyte(iobase + 2, 0x48); // read byte command
- // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + // time limit to avoid hanging for unexpected error status + limit = __rdtsc() + 2000000000 / 10; + for (;;) { + status = __inbyte(iobase); + if (__rdtsc() > limit) + break; + if ((status & 2) == 0) + continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) + continue; // HostBusy set, keep waiting break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = __inbyte(iobase + 5); + if (status == 2) + status = 0; // check for done with no errors return status; }
@@ -61,28 +64,30 @@ * readSmbusByte - read a single SPD byte from the default offset * this function is faster function readSmbusByteData */ - -static int readSmbusByte (int iobase, int address, char *buffer) +static int readSmbusByte(int iobase, int address, char *buffer) { unsigned int status; UINT64 limit;
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + __outbyte(iobase + 0, 0xff); // clear error status + __outbyte(iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + limit = __rdtsc() + 2000000000 / 10; + for (;;) { + status = __inbyte(iobase); + if (__rdtsc() > limit) + break; + if ((status & 2) == 0) + continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) + continue; // HostBusy set, keep waiting break; }
- buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + buffer[0] = __inbyte(iobase + 5); + if (status == 2) + status = 0; // check for done with no errors return status; }
@@ -94,17 +99,16 @@ * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count) { int index, error;
printk(BIOS_SPEW, "-------------READING SPD-----------\n"); printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n", - iobase, SmbusSlaveAddress, count); + iobase, SmbusSlaveAddress, count);
/* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + error = readSmbusByteData(iobase, SmbusSlaveAddress, buffer, 0);
if (error) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); @@ -112,9 +116,9 @@ }
/* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + for (index = 1 ; index < count ; index++) { + error = readSmbusByte(iobase, SmbusSlaveAddress, + &buffer[index]); if (error) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -126,22 +130,23 @@ return 0; }
-static void writePmReg (int reg, int data) +static void writePmReg(int reg, int data) { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); + __outbyte(PM_INDEX, reg); + __outbyte(PM_DATA, data); }
-static void setupFch (int ioBase) +static void setupFch(int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + writePmReg(0x2d, ioBase >> 8); + writePmReg(0x2c, ioBase | 1); + /* set SMBus clock to 400 KHz */ + __outbyte(ioBase + 0x0e, 66000000 / 400000 / 4); }
int hudson_readSpd(int spdAddress, char *buf, size_t len) { - int ioBase = 0xB00; - setupFch (ioBase); - return readspd (ioBase, spdAddress, buf, len); + int ioBase = 0xb00; + setupFch(ioBase); + return readspd(ioBase, spdAddress, buf, len); } diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index cf95418..5a646a6 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -110,7 +110,8 @@ smi_write32(0x90, status); }
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(unsigned int node, + smm_state_save_area_t *state_save) { const uint16_t smi_src = smi_read16(0x94);
diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 5d88204..7919207 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -14,10 +14,11 @@ */
#include <console/uart.h> +#include <soc/hudson.h>
uintptr_t uart_platform_base(int idx) { - return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); + return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); }
unsigned int uart_platform_refclk(void)
-
Marshall Dawson (Code Review)