[M] Change in coreboot[main]: mb/google/fatcat: Enable DPTF

[Jérémy Compostella (Code Review)]

Attention is currently required from: Pranava Y N, Subrata Banik.

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email )

Change subject: mb/google/fatcat: Enable DPTF
......................................................................

mb/google/fatcat: Enable DPTF

Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97
Signed-off-by: Jeremy Compostella 
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
2 files changed, 130 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85457/1

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index a67ea3b..bee6d71 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -5,6 +5,7 @@
    select BOARD_ROMSIZE_KB_32768
    select DRIVERS_I2C_GENERIC
    select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
    select DRIVERS_INTEL_MIPI_CAMERA
    select DRIVERS_INTEL_PMC
    select DRIVERS_INTEL_SOUNDWIRE
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index fba49fd..10a351a 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -137,11 +137,140 @@
    	},
    }"

+	# Enable DPTF
+	register "dptf_enable" = "true"
+
    device domain 0 on
    	device ref igpu on
    		probe DISPLAY DISPLAY_PRESENT
    	end

+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DDR_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""wwan""
+
+				## Active Policy
+				# FIXME: below values are initial reference values only
+				register "policies.active" = "{
+						[0] = {
+							.target = DPTF_TEMP_SENSOR_0,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[1] = {
+							.target = DPTF_TEMP_SENSOR_1,
+							.thresholds = {
+									TEMP_PCT(70, 97),
+									TEMP_PCT(65, 90),
+									TEMP_PCT(60, 80),
+									TEMP_PCT(55, 75),
+									TEMP_PCT(50, 65),
+									TEMP_PCT(45, 45),
+									TEMP_PCT(43, 30),
+								}
+							},
+						[2] = {
+							.target = DPTF_TEMP_SENSOR_2,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 50),
+								}
+							},
+						[3] = {
+							.target = DPTF_TEMP_SENSOR_3,
+							.thresholds = {
+									TEMP_PCT(75, 90),
+									TEMP_PCT(70, 80),
+									TEMP_PCT(65, 70),
+									TEMP_PCT(60, 60),
+									TEMP_PCT(55, 50),
+									TEMP_PCT(50, 40),
+									TEMP_PCT(45, 30),
+								}
+							}
+				}"
+
+				## Passive Policy
+				# TODO: below values are initial reference values only
+				register "policies.passive" = "{
+						[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+						[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+						[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 80, 5000),
+						[3] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_2, 75, 5000),
+						[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
+				}"
+
+				## Critical Policy
+				# TODO: below values are initial reference values only
+				register "policies.critical" = "{
+						[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),
+						[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+						[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+						[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+						[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+						.pl1 = {
+							.min_power = 25000,
+							.max_power = 25000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+						.pl2 = {
+							.min_power = 95000,
+							.max_power = 95000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+						[0] = { 255, 3000 },
+						[1] = {  24, 1500 },
+						[2] = {  16, 1000 },
+						[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+						[0] = {  90, 6700, 220, 2200, },
+						[1] = {  80, 5800, 180, 1800, },
+						[2] = {  70, 5000, 145, 1450, },
+						[3] = {  60, 4900, 115, 1150, },
+						[4] = {  50, 3838,  90,  900, },
+						[5] = {  40, 2904,  55,  550, },
+						[6] = {  30, 2337,  30,  300, },
+						[7] = {  20, 1608,  15,  150, },
+						[8] = {  10,  800,  10,  100, },
+						[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
+
    	device ref ipu on
    		chip drivers/intel/mipi_camera
    			register "acpi_uid" = "0x50000"