Change in coreboot[master]: [UNTESTED] soc/amd: add and use fch_enable_hpet_decode

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50512 )

Change subject: [UNTESTED] soc/amd: add and use fch_enable_hpet_decode
......................................................................

[UNTESTED] soc/amd: add and use fch_enable_hpet_decode

On Picasso we missed setting this bit. Stoneyridge and Cezanne have the
HPET decode enable bit in the same position in the same register. In the
ACPI table entry written by southbridge_write_acpi_tables the HPET entry
gets added, so we need to enable the decode.

Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held 
---
M src/soc/amd/cezanne/fch.c
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/picasso/fch.c
M src/soc/amd/stoneyridge/southbridge.c
5 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/50512/1

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 3e2eade..8a9b379 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -52,6 +52,8 @@
 void fch_init(void *chip_info)
 {
    fch_init_acpi_ports();
+
+	fch_enable_hpet_decode();
 }

void fch_final(void *chip_info)
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index 1cacd44..b4745b7 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -74,6 +74,11 @@
    pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN);
 }

+void fch_enable_hpet_decode(void)
+{
+	pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | HPET_FED0_EN);
+}
+
 /* PM registers are accessed a byte at a time via CD6/CD7 */
 uint8_t pm_io_read8(uint8_t reg)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 4b80a28..30184a5 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -17,6 +17,7 @@
 #define PM_DECODE_EN			0x00
 #define   SMBUS_ASF_IO_BASE_SHIFT	8
 #define   SMBUS_ASF_IO_BASE_MASK	(0xff << SMBUS_ASF_IO_BASE_SHIFT)
+#define   HPET_FED0_EN			(1 << 6)
 #define   SMBUS_ASF_IO_EN		(1 << 4)
 #define   CF9_IO_EN			(1 << 1)
 #define   LEGACY_IO_EN			(1 << 0)
@@ -75,6 +76,7 @@
 void fch_enable_cf9_io(void);
 void fch_enable_legacy_io(void);
 void fch_io_enable_legacy_io(void);
+void fch_enable_hpet_decode(void);

/* Access PM registers using IO cycles */
 uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index 5d62e8e..6dcb68e 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -235,6 +235,8 @@
    sb_clk_output_48Mhz();

sb_rfmux_config_override();
+
+	fch_enable_hpet_decode();
 }

void fch_final(void *chip_info)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 161e3e8..e6e4ca9 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -401,6 +401,8 @@
 void fch_init(void *chip_info)
 {
    fch_init_acpi_ports();
+
+	fch_enable_hpet_decode();
 }

static void set_sb_aoac(struct aoac_devs *aoac)