Change in coreboot[master]: nb/intel/sandybridge: Support setting PCI bars above 4G

[Arthur Heymans (Code Review)]

Attention is currently required from: Angel Pons, Patrick Rudolph.
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/51060

to look at the new patch set (#2).

Change subject: nb/intel/sandybridge: Support setting PCI bars above 4G
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nb/intel/sandybridge: Support setting PCI bars above 4G

With PCI BARs above 4G without that region being present in the
_SB.PCI0._CRS, Linux relocates and possibly resizes the BAR below 4G.

Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/sandybridge/acpi/hostbridge.asl
M src/northbridge/intel/sandybridge/northbridge.c
M src/soc/intel/common/block/systemagent/systemagent.c
3 files changed, 54 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/51060/2