Change in coreboot[master]: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Hello Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35227
to review the following change.
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.
Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: sridhar sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7697a4a..9585a09 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,10 +69,18 @@
#define HECI_OP_MODE_SEC_OVERRIDE 5
+/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + static struct cse_device { uintptr_t sec_bar; } g_cse;
+/* HFSTS1 */ union me_hfs { u32 data; struct { @@ -595,6 +603,54 @@ return reg; }
+/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be GLOBAL_RESET/ + * HOST_RESET_ONLY/HOST_RESET_ONLY. + */ +int send_heci_reset_req_message(u8 rst_type) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __packed reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __packed; + struct reset_message msg = { + .group_id = MKHI_GROUP_ID_CBM, + .cmd = MKHI_GLOBAL_RESET_REQ, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = rst_type + }; + size_t reply_size; + + if (!((rst_type == GLOBAL_RESET) + || (rst_type == HOST_RESET_ONLY) + || (rst_type == CSE_RESET_ONLY))) { + return -1; + } + + heci_reset(); + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + printk(BIOS_ERR, "HECI Global Reset(type=%d) Command\n", rst_type); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + if (status != 1) + return -1; + + printk(BIOS_DEBUG, "HECI GBL RST success!\n"); + return 0; +}
#if ENV_RAMSTAGE
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 82e07cf..ceeca88e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -70,6 +70,13 @@ */ int wait_cse_rec(void);
+/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be + * GLOBAL_RESET/HOST_RESET_ONLY/HOST_RESET_ONLY. + * Returns -1 on failure a 0 on success. + */ +int send_heci_reset_req_message(u8 rst_type); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07
@@ -83,4 +90,11 @@ PCI_ME_HFSTS6 = 0x6C, };
+ +/* Command GLOBAL_RESET_REQ Reset Types */ +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 + + #endif // SOC_INTEL_COMMON_MSR_H
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35227 )
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Patch Set 1:
(51 comments)
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 612: int status; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 613: struct reset_reply { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 614: u8 group_id; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 614: u8 group_id; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 615: u8 command; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 615: u8 command; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 616: u8 reserved; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 616: u8 reserved; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 617: u8 result; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 617: u8 result; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 618: } __packed reply; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 619: struct reset_message { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 620: u8 group_id; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 620: u8 group_id; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 621: u8 cmd; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 621: u8 cmd; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 622: u8 reserved; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 622: u8 reserved; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 623: u8 result; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 623: u8 result; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 624: u8 req_origin; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 624: u8 req_origin; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 625: u8 reset_type; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 625: u8 reset_type; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 626: } __packed; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 627: struct reset_message msg = { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 628: .group_id = MKHI_GROUP_ID_CBM, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 628: .group_id = MKHI_GROUP_ID_CBM, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 629: .cmd = MKHI_GLOBAL_RESET_REQ, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 629: .cmd = MKHI_GLOBAL_RESET_REQ, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 630: .req_origin = GR_ORIGIN_BIOS_POST, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 630: .req_origin = GR_ORIGIN_BIOS_POST, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 631: .reset_type = rst_type code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 631: .reset_type = rst_type please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 632: }; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 633: size_t reply_size; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 635: if (!((rst_type == GLOBAL_RESET) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 635: if (!((rst_type == GLOBAL_RESET) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 638: return -1; Statements should start on a tabstop
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 639: } please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 641: heci_reset(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 643: reply_size = sizeof(reply); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 644: memset(&reply, 0, reply_size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 646: printk(BIOS_ERR, "HECI Global Reset(type=%d) Command\n", rst_type); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 647: status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 648: if (status != 1) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 648: if (status != 1) suspect code indent for conditional statements (7, 14)
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 649: return -1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 649: return -1; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 651: printk(BIOS_DEBUG, "HECI GBL RST success!\n"); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35227/1/src/soc/intel/common/block/... PS1, Line 652: return 0; please, no spaces at the start of a line
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35227
to look at the new patch set (#2).
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.
* Fix all comments on indentation
Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: sridhar sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/2
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35227 )
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35227/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35227/2//COMMIT_MSG@12 PS2, Line 12: * Fix all comments on indentation not required, the gerrit patchset history knows what you have done with the patch
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35227
to look at the new patch set (#3).
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.
Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/3
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35227
to look at the new patch set (#10).
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.
TEST=Verfied sending HECI reset messsage on CML RVP & Hatch board
Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/10
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35227 )
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35227/11/src/soc/intel/common/block... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35227/11/src/soc/intel/common/block... PS11, Line 83: /* HFSTS1 */ unrelated change?
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35227
to look at the new patch set (#13).
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.
TEST=Verfied sending HECI reset messsage on CML RVP & Hatch board
Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/13
Sridhar Siricilla has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35227 )
Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Removed reviewer Patrick Rudolph.
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Removed reviewer Subrata Banik.
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Removed reviewer Aamir Bohra.
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
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Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ......................................................................
Removed reviewer Paul Menzel.
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