Change in coreboot[master]: soc/intel/alderlake: Enable VT-d

[Subrata Banik (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 )

Change subject: soc/intel/alderlake: Enable VT-d
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Patch Set 5:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/51849/comment/b1a80270_8f9a61bd 
PS5, Line 204: 		#if (GFXVT_BASE_ADDRESS == 0)
             : 			#error "Error: GFXVT_BASE_ADDRESS should be non-zero for enabling VT-d!"
             : 		#endif
> I think it's OK to have these as runtime checks, for example: […]

@Tim, the reason, i have asked is to avoid additional debug time, if you have Vtd for IGD enable and base is zero, it cause hang. Atleast in this static method we save debug time and failure ?