Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Programm CxODT value for each channel ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i945... File src/northbridge/intel/i945/raminit.c:
https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i945... PS22, Line 2473: MCHBAR32(C1ODT)
High-speed electrical signalling is very cursed. If there is a bifurcation on a high-speed trace, the electrical signals will propagate across the two branches and go back after reflecting at the end of the path. Because of propagation delays, the reflected signals are not necessarily in phase with the original signal, so their superposition seriously degrades signal quality. To mitigate this problem, chips with high-speed interfaces often have on-die termination (ODT) resistors.
That, and reflections anyway. You don't need bifurcation to get into trouble. A reflected signal is always bad.
In the case of DRAM, since a chip does not care about the values on high-speed lanes when it is not selected, ODT can be enabled to dissipate the energy of signals that would otherwise be ignored and reflect. On consumer mainboards, these bifurcations only happen on memory topologies with two or more DIMMs per channel. This would explain the original code: Calistoga can only have one DIMM per channel. However, Lakeport can have two DIMMs per channel, and thus a need for ODT. And, of course, it does not make sense to enable ODT when only one DIMM is installed, as the DIMM is never unselected when the bus is active.
Therefore, ODT should only be enabled when both DIMMs are present on a channel.
Um, why does it need 3 bits to disable something? I don't think this disables ODT. It rather configures something, e.g. what rank should enable ODT or maybe it adapts the resistance on the MCH side.
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Nico Huber (Code Review)