Change in coreboot[master]: Revert "mb/google/poppy/variants/atlas: enable camera power and relea...

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28072 )

Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"
......................................................................

Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"

This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4.

Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.

BUG=b:80106316,b:111141128

Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali 
Reviewed-on: https://review.coreboot.org/28072
Reviewed-by: Furquan Shaikh 
Reviewed-by: Ping-chung Chen 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/poppy/variants/atlas/gpio.c
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Ping-chung Chen: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c
index c0ef9ef..5f1a1f5 100644
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -175,7 +175,7 @@
    /* D7  : ISH_I2C1_SDA ==> SPKR_IRQ_L */
    PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST),
    /* D8  : ISH_I2C1_SCL ==> EN_CAMERA_PWR */
-	PAD_CFG_GPO(GPP_D8, 1, DEEP),
+	PAD_CFG_GPO(GPP_D8, 0, DEEP),
    /* D9  : ISH_SPI_CS# ==> ISH_SPI_CS_L */
    PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1),
    /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */
@@ -189,9 +189,9 @@
    /* D16 : ISH_UART0_CTS# ==> NC */
    PAD_CFG_NC(GPP_D16),
    /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */
-	PAD_CFG_GPO(GPP_D17, 1, DEEP),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
    /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */
-	PAD_CFG_GPO(GPP_D18, 1, DEEP),
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
    /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
    PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
    /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */