[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82177?usp=email )

Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
......................................................................

soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility

This commit updates the type definitions for FSP parameters in the
Meteor Lake platform to ensure compatibility with the FSP2.4
specification, that supports 64-bit builds for the first time and
this  also ensures that parameter types works for both 32-bit
and 64-bit builds.

- In fsp_params.c, FSPS_ARCH_UPD macro is changed to
  FSPS_ARCHx_UPD which supports FSP2.4 and older specifications.
  Special handling is added for FspEventHandler assignment to handle
  as the variable type is different in both cases.

- In meminit.c, the type for SPD pointers is changed from uint32_t
  to efi_uintn_t to support both 32-bit and 64-bit builds.

BUG=b:329034258
TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex)

Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a
Signed-off-by: Appukuttan V K 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177
Reviewed-by: Dinesh Gehlot 
Reviewed-by: Kapil Porwal 
Reviewed-by: Subrata Banik 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/meteorlake/meminit.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
3 files changed, 15 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index a02d4b9..0ac3b48 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -703,7 +703,7 @@
    printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 }

-static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
+static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg)
 {
    /*
     * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit
@@ -713,8 +713,14 @@
    /* Assign FspEventHandler arch Upd to use coreboot debug event handler */
    if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
    		 CONFIG(FSP_ENABLE_SERIAL_DEBUG))
+
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
    	s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER)
    			fsp_debug_event_handler;
+#else
+		s_arch_cfg->FspEventHandler = (EFI_PHYSICAL_ADDRESS)
+				fsp_debug_event_handler;
+#endif
 }

static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
@@ -822,7 +828,7 @@
 {
    struct soc_intel_meteorlake_config *config;
    FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
-	FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
+	FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;

config = config_of_soc();
    arch_silicon_init_params(s_arch_cfg);
diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c
index fa7e1fd..32ab358 100644
--- a/src/soc/intel/meteorlake/meminit.c
+++ b/src/soc/intel/meteorlake/meminit.c
@@ -77,7 +77,7 @@

static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
-	uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
+	efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
    	[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
    	[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
    	[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
@@ -106,7 +106,7 @@
    	bool enable_channel = 0;

for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
-			uint32_t *spd_ptr = spd_upds[ch][dimm];
+			efi_uintn_t *spd_ptr = spd_upds[ch][dimm];

*spd_ptr = data->spd[ch][dimm];
    		if (*spd_ptr)
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index caf57a3..0f44d65 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -446,7 +446,7 @@
 #define VGA_INIT_CONTROL_TEAR_DOWN	BIT(1)

static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
-				   FSPM_ARCH_UPD *arch_upd)
+				   FSPM_ARCHx_UPD *arch_upd)
 {
    void *vbt;
    size_t vbt_size;
@@ -485,22 +485,22 @@
    elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);

m_cfg->VgaInitControl = vga_init_control;
-	m_cfg->VbtPtr = (UINT32)vbt;
+	m_cfg->VbtPtr = (efi_uintn_t)vbt;
    m_cfg->VbtSize = vbt_size;
    m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	m_cfg->VgaMessage = (UINT32)text;
+	m_cfg->VgaMessage = (efi_uintn_t)text;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    const struct soc_intel_meteorlake_config *config;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-	FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
+	FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;

if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
    	if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
    		enum fsp_log_level log_level = fsp_map_console_log_level();
-			arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
+			arch_upd->FspEventHandler = (efi_uintn_t)((FSP_EVENT_HANDLER *)
    				fsp_debug_event_handler);
    		/* Set Serial debug message level */
    		m_cfg->PcdSerialDebugLevel = log_level;