Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42886 )
Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ......................................................................
soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000
This places EARLY_RESERVED_DRAM_BASE right after the Option ROM. This closes the ~31 MiB gap between the Option ROM and Early RAM.
[ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000003bcfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000003bd000-0x00000000cc51bfff] usable [ 0.000000] BIOS-e820: [mem 0x00000000cc51c000-0x00000000cd7fffff] type 16 [ 0.000000] BIOS-e820: [mem 0x00000000cd800000-0x00000000cfffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000042f33ffff] usable [ 0.000000] BIOS-e820: [mem 0x000000042f340000-0x000000042fffffff] reserved
BUG=b:159081993 TEST=Boot picasso trembyle and run suspend_stress_test a few times.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I5944abce19f17458ea3017d04f6dfdfe8e8050bf --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 2 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42886/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9630ad3..0d87c1f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -63,7 +63,7 @@
config EARLY_RESERVED_DRAM_BASE hex - default 0x2000000 + default 0x100000 help This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). @@ -77,14 +77,14 @@
config PSP_APOB_DRAM_ADDRESS hex - default 0x2001000 + default 0x101000 help Location in DRAM where the PSP will copy the AGESA PSP Output Block.
config PSP_SHAREDMEM_BASE hex - default 0x2011000 if VBOOT + default 0x111000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies @@ -111,7 +111,7 @@
config BOOTBLOCK_ADDR hex - default 0x2030000 + default 0x120000 help Sets the address in DRAM where bootblock should be loaded.
@@ -126,7 +126,7 @@ config X86_RESET_VECTOR hex depends on ARCH_X86 - default 0x203fff0 + default 0x12fff0 help Sets the reset vector within bootblock where x86 starts execution. Reset vector is supposed to live at offset -0x10 from end of @@ -134,7 +134,7 @@
config ROMSTAGE_ADDR hex - default 0x2040000 + default 0x130000 help Sets the address in DRAM where romstage should be loaded.
@@ -146,7 +146,7 @@
config FSP_M_ADDR hex - default 0x20C0000 + default 0x1B0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. @@ -160,7 +160,7 @@ config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2140000 + default 0x230000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..e94c3ba 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -39,7 +39,7 @@ * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR * | Unused hole | - * | (86KiB) | + * | (21KiB) | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42886 )
Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42886/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42886/1//COMMIT_MSG@10 PS1, Line 10: closes the ~31 MiB gap between the Option ROM and Early RAM. I thought the gap was left so there is a least a chance to run arbitrary OS' and payloads. Do I miss something?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42886 )
Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42886/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42886/1//COMMIT_MSG@10 PS1, Line 10: closes the ~31 MiB gap between the Option ROM and Early RAM.
I thought the gap was left so there is a least a chance to run arbitrary […]
Yes, that was the original intent to leave that hole before EARLY_RESERVED_DRAM_BASE.
Attention is currently required from: Nico Huber, Raul Rangel, Furquan Shaikh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42886 )
Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/42886/comment/6b2b18e1_5ce5e968 PS1, Line 10: closes the ~31 MiB gap between the Option ROM and Early RAM.
Yes, that was the original intent to leave that hole before EARLY_RESERVED_DRAM_BASE.
What changed to make this unnecessary?
https://review.coreboot.org/c/coreboot/+/42886/comment/e309a264_566d0e7a PS1, Line 21: [ 0.000000] BIOS-e820: [mem 0x000000042f340000-0x000000042fffffff] reserved You could remove the timestamps to make the lines fit in 72 characters
Raul Rangel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42886 )
Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ......................................................................
Abandoned
This change is not needed.
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Nico Huber (Code Review)
-
Raul Rangel (Code Review)