Change in coreboot[master]: ec/google/chromeec: don't put empty block in SSDT

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

ec/google/chromeec: don't put empty block in SSDT

Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents and empty scope from being generated on
devices without any SB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).

Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.

Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier 
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 6 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39665/1

diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 4dfd44b..47d60d5 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -177,19 +177,14 @@
    }
 }

-static void fill_ssdt_typec_device(struct device *dev)
+static void fill_ssdt_typec_device(int num_ports)
 {
    struct usb_pd_port_caps port_caps;
    char con_name[] = "CONx";
    struct acpi_dp *dsd;
-	int num_ports;
    int rv;
    int i;

-	rv = google_chromeec_get_num_pd_ports(&num_ports);
-	if (rv)
-		return;
-
    acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME);
    acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID);
    acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller "
@@ -220,8 +215,12 @@

void google_chromeec_fill_ssdt_generator(struct device *dev)
 {
+	int num_ports;
+	if (google_chromeec_get_num_pd_ports(&num_ports))
+		return;
+
    /* Reference the existing device's scope */
    acpigen_write_scope(acpi_device_path(dev));
-	fill_ssdt_typec_device(dev);
+	fill_ssdt_typec_device(num_ports);
    acpigen_pop_len(); /* Scope */
 }

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 1: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 1: Code-Review+1

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39665/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39665/1//COMMIT_MSG@12 
PS1, Line 12: SB
USB?

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39665

to look at the new patch set (#2).

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

ec/google/chromeec: don't put empty block in SSDT

Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents and empty scope from being generated on
devices without any USB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).

Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.

Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier 
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 6 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39665/2

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39665/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39665/1//COMMIT_MSG@12 
PS1, Line 12: SB
> USB?

Done

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 2: Code-Review+2

[Matt DeVillier (Code Review)]

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39665

to look at the new patch set (#3).

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

ec/google/chromeec: don't put empty block in SSDT

Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents an empty scope from being generated on
devices without any USB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).

Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.

Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier 
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 6 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39665/3

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

Patch Set 3:

Thanks for keeping us honest, Matt 😊

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39665 )

Change subject: ec/google/chromeec: don't put empty block in SSDT
......................................................................

ec/google/chromeec: don't put empty block in SSDT

Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents an empty scope from being generated on
devices without any USB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).

Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.

Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Angel Pons 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 6 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 4dfd44b..47d60d5 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -177,19 +177,14 @@
    }
 }

-static void fill_ssdt_typec_device(struct device *dev)
+static void fill_ssdt_typec_device(int num_ports)
 {
    struct usb_pd_port_caps port_caps;
    char con_name[] = "CONx";
    struct acpi_dp *dsd;
-	int num_ports;
    int rv;
    int i;

-	rv = google_chromeec_get_num_pd_ports(&num_ports);
-	if (rv)
-		return;
-
    acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME);
    acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID);
    acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller "
@@ -220,8 +215,12 @@

void google_chromeec_fill_ssdt_generator(struct device *dev)
 {
+	int num_ports;
+	if (google_chromeec_get_num_pd_ports(&num_ports))
+		return;
+
    /* Reference the existing device's scope */
    acpigen_write_scope(acpi_device_path(dev));
-	fill_ssdt_typec_device(dev);
+	fill_ssdt_typec_device(num_ports);
    acpigen_pop_len(); /* Scope */
 }