[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, TangYiwei, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )

Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes
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Patch Set 21:

(4 comments)

File src/soc/intel/xeon_sp/chip_gen6.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/b15eb13a_d214a524 :
PS18, Line 145: 	soc_create_fsp24_domains(dp, upstream, sr, DOMAIN_TYPE_IOAT, pci_segment_group);
> This will work, but I realized that in SPR, the domain names will be conflict with the static SSDT A […]

Since the code base changes a lot. Let me close this first and please open new discussion if any. Thanks!

File src/soc/intel/xeon_sp/chip_gen6.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/ac59dc7b_d61aece4 :
PS21, Line 34: }
> Note, you could avoid the late HOB lookup by adding the resources already […]

Good suggestion, I will have a patch to modify gen1 and gen6 together for this.

https://review.coreboot.org/c/coreboot/+/81316/comment/ad2ea755_0e87b7c2 :
PS21, Line 57: 			res->flags = IORESOURCE_SUBTRACTIVE;
> In hardware, there's virtually always only one subtractive resource of a type. […]

You are right. This is a bug, fixed.

https://review.coreboot.org/c/coreboot/+/81316/comment/99966c82_180cc69f :
PS21, Line 119: void iio_pci_domain_read_resources(struct device *dev)
> Why is this an external API?

Good catch, fixed.