Change in coreboot[master]: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin.
Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58935 )

Change subject: soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder
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soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folder

Add NOR-Flash GPIO setting in mt8186/spi.c.

TEST=boot to romstage
BUG=b:202871018

Signed-off-by: Rex-BC Chen 
Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337
---
M src/soc/mediatek/mt8186/include/soc/spi.h
M src/soc/mediatek/mt8186/spi.c
2 files changed, 47 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/58935/1

diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h
index cf64660..fbf3995 100644
--- a/src/soc/mediatek/mt8186/include/soc/spi.h
+++ b/src/soc/mediatek/mt8186/include/soc/spi.h
@@ -10,4 +10,12 @@

#include <spi-generic.h>

+enum {
+	SPI_NOR_GPIO_SET0 = 0,
+	SPI_NOR_GPIO_SET1,
+	SPI_NOR_GPIO_SET_NUM,
+};
+
+void mtk_snfc_init(int gpio_set);
+
 #endif
diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c
index e72b50f..7adb4b3 100644
--- a/src/soc/mediatek/mt8186/spi.c
+++ b/src/soc/mediatek/mt8186/spi.c
@@ -5,11 +5,50 @@
  * Chapter number: 5.6, 5.8
  */

+#include <assert.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
 #include <soc/flash_controller_common.h>
+#include <soc/gpio.h>
 #include <soc/spi.h>

+struct pad_func {
+	gpio_t gpio;
+	u8 func;
+};
+
+#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
+
+static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = {
+	/* GPIO 36 ~ 39 */
+	{
+		PAD_FUNC(SPI0_CLK, SPINOR_CK),
+		PAD_FUNC(SPI0_CSB, SPINOR_CS),
+		PAD_FUNC(SPI0_MO, SPINOR_IO0),
+		PAD_FUNC(SPI0_MI, SPINOR_IO1),
+	},
+	/* GPIO 61 ~ 64 */
+	{
+		PAD_FUNC(TDM_RX_BCK, SPINOR_CK),
+		PAD_FUNC(TDM_RX_MCLK, SPINOR_CS),
+		PAD_FUNC(TDM_RX_DATA0, SPINOR_IO0),
+		PAD_FUNC(TDM_RX_DATA1, SPINOR_IO1),
+	},
+};
+
+void mtk_snfc_init(int gpio_set)
+{
+	const struct pad_func *ptr = NULL;
+
+	assert(gpio_set < SPI_NOR_GPIO_SET_NUM);
+
+	ptr = nor_pinmux[gpio_set];
+	for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) {
+		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+	}
+}
+
 static const struct spi_ctrlr spi_flash_ctrlr = {
    .max_xfer_size = 65535,
    .flash_probe = mtk_spi_flash_probe,