[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Fred Reitberger, Felix Held.
Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ......................................................................
Patch Set 22:
(2 comments)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/af7a6d09_ad09c0c7 PS16, Line 393: #else
Since many default and low/now battery entries duplicated, do we need to expand the parameters for low/now battery in chip.h?
Only the values that are different between these 2 modes need separate entries. Otherwise, they should use the same values to remove any duplication.
Since the default table (Table A) already has everything defined in the structs, the next step is to fill out `src/mainboard/google/skyrim/variants/skyrim/overridetree.cb` with any missing values. Otherwise, the default and low/no battery tables will contain unknown/invalid values which will be written whenever SB.DPTC() is called. This is where you'll need AMD's input. Alternatively, you may be able to use `agt` to see what the default values are.
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/27d45719_3168221e PS18, Line 269: /* Normal mode DPTC values. */
This is (or at least should be) a duplicate of the default table that's already defined below, and s […]
Done
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Tim Van Patten (Code Review)