Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 )

Change subject: soc/intel/common/block/cse: Add boot partition related APIs
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Patch Set 26:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35402/25/src/soc/intel/common/block... 
File src/soc/intel/common/block/include/intelblocks/cse.h:

https://review.coreboot.org/c/coreboot/+/35402/25/src/soc/intel/common/block... 
PS25, Line 155:  * Otherwise, it contains only 2 partitions(BP1+BP3)
> Done

Thanks. Alas, I still don't get it. Below it says BP3 is loaded by BP2.
So in the absence of BP2 (no-redundancy case), how is BP3 used?

Or does the no-redundancy case imply that the BP2 firmware is used
with BP1? Wouldn't it make more sense then, to say no-redundancy is
BP2+BP3? I guess it would be clearer if we would give them names,
not numbers.

Is there an Intel document describing this? I couldn't find anything
about BPs in Intel's ME BIOS Specifications.

My current interpretation is as follows:
* No-redundancy: 1st partition (Boot+AppLoader), 2nd partition (Apps)
* Redundancy: 1st partition (Boot), 2nd partition (Boot+AppLoader), 3rd partition (Apps)

Does that make any sense?