Change in coreboot[master]: soc/intel/alderlake: Fix overlapping memory address used for early GS...
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47644 )
Change subject: soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars ......................................................................
soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
TEST=none
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47644/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..0db8e1c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -159,7 +159,7 @@
config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47644 )
Change subject: soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars ......................................................................
Patch Set 1:
Aamir, I don't have alderlake platform to check, can you please help check?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47644 )
Change subject: soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47644 )
Change subject: soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars ......................................................................
soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
TEST=none
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..0db8e1c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -159,7 +159,7 @@
config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
-
Bora Guvendik (Code Review) -
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)