Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18526 )
Change subject: binaryPI: Drop CAR teardown without POSTCAR_STAGE ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/18526/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/18526/8//COMMIT_MSG@11 PS8, Line 11: POSTCAR_STAGE now. I need to add references to changes and discussions. This is really a revert for the gcccar.inc parts, to put it back into the state AMD originally shipped it.
https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/00630... File src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc:
https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/00630... PS8, Line 1550: * AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine : * should only be executed on the BSP
Is there some documentation of what is run on AP's by AGESA and in what state those are? The code be […]
The source.
https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/00630... PS8, Line 1574: : # Set lower 640K MTRRs for Write-Back memory caching : mov $AMD_MTRR_FIX64k_00000, %ecx : mov $0x1E1E1E1E, %eax : mov %eax, %edx : _WRMSR # 0 - 512K = WB Mem : mov $AMD_MTRR_FIX16k_80000, %ecx : _WRMSR
Is this still needed with relocatable ramstage?
Perhaps not. I am not going to open up the MTRR mess here. This commit is really a revert of changes that happened at SAGE for coreboot deployment. CAR teardown used to happen with a non-empty C stack so invd did not work.
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Kyösti Mälkki (Code Review)