[S] Change in coreboot[master]: mb/google/myst: Store XHCI PCI resources

[Jon Murphy (Code Review)]

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74281 )

Change subject: mb/google/myst: Store XHCI PCI resources
......................................................................

mb/google/myst: Store XHCI PCI resources

Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.

BUG=b:277273428
TEST=builds

Signed-off-by: Jon Murphy 
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
---
M src/mainboard/google/myst/mainboard.c
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74281/1

diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c
index 4ac41da..2da7068 100644
--- a/src/mainboard/google/myst/mainboard.c
+++ b/src/mainboard/google/myst/mainboard.c
@@ -3,8 +3,10 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/psp.h>
+#include <amdblocks/xhci.h>
 #include <baseboard/variants.h>
 #include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <drivers/i2c/tpm/chip.h>
 #include <soc/acpi.h>
@@ -93,6 +95,11 @@
    pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
 }

+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_xhci_store_resources(slots, size);
+}
+
 struct chip_operations mainboard_ops = {
    .init = mainboard_init,
    .enable_dev = mainboard_enable,