Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage - coreboot-gerrit

22 Nov 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 )
Change subject: soc/amd/cezanne/romstage: Call preload_ramstage
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Patch Set 5:
(1 comment)
File src/soc/amd/cezanne/fsp_m_params.c:
https://review.coreboot.org/c/coreboot/+/58983/comment/0525082f_d3ae3b39 
PS5, Line 181: preload_ramstage();
...
Why here and why not in soc/amd/cezanne/romstage. […]
I was hoping the comment would explain it :(
We want FSP-M to be free'd from the CBFS buffer before calling this.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51
Gerrit-Change-Number: 58983
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