[S] Change in coreboot[master]: mb/system76/adl-p: Disable SATA DevSlp

[Tim Crawford (Code Review)]

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70100 )

Change subject: mb/system76/adl-p: Disable SATA DevSlp
......................................................................

mb/system76/adl-p: Disable SATA DevSlp

After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in
system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for
modern standby detection"), DevSlp blocks suspend entry. Disable it
until it is fixed.

Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da
Signed-off-by: Tim Crawford 
---
M src/mainboard/system76/adl-p/devicetree.cb
1 file changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/70100/1

diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb
index 6a9f362..c7085b4 100644
--- a/src/mainboard/system76/adl-p/devicetree.cb
+++ b/src/mainboard/system76/adl-p/devicetree.cb
@@ -73,7 +73,8 @@
    	device ref sata on
    		register "sata_salp_support" = "1"
    		register "sata_ports_enable[1]" = "1" # SSD1
-			register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
+			# FIXME: DevSlp breaks S0ix
+			#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
    	end
    	device ref pch_espi on
    		register "gen1_dec" = "0x00040069" # EC PM channel