HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31408
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
nb/intel/i945: Use big enough type for left-shift
Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c 4 files changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31408/1
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 053815b..3fc1483 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -41,15 +41,15 @@
switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); max_buses = 256; break; case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); max_buses = 128; break; case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); max_buses = 64; break; default: // RSVD diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b82812e..fb504af 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -316,7 +316,7 @@ printk(BIOS_DEBUG, "ok\n");
/* Now enable VC1 */ - EPBAR32(EPVC1RCTL) |= (1 << 31); + EPBAR32(EPVC1RCTL) |= (1U << 31);
printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -359,7 +359,7 @@
reg32 = RCBA32(V1CTL); reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); - reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); + reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1U << 31); RCBA32(V1CTL) = reg32;
RCBA32(ESD) |= (2 << 16); @@ -408,7 +408,7 @@ DMIBAR32(DMIVC1RCTL) = reg32;
/* Now enable VC1 */ - DMIBAR32(DMIVC1RCTL) |= (1 << 31); + DMIBAR32(DMIVC1RCTL) |= (1U << 31);
printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ @@ -485,8 +485,8 @@ reg32 |= (0x02 << 26); DMIBAR32(0x200) = reg32;
- DMIBAR32(DMIDRCCFG) &= ~(1 << 31); - DMIBAR32(DMICTL2) |= (1 << 31); + DMIBAR32(DMIDRCCFG) &= ~(1U << 31); + DMIBAR32(DMICTL2) |= (1U << 31);
if (i945_silicon_revision() >= 3) { reg32 = DMIBAR32(0xec0); @@ -762,11 +762,11 @@ pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); - reg32 &= ~(1 << 31); + reg32 &= ~(1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); - reg32 |= (1 << 31); + reg32 |= (1U << 31); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32);
if (i945_silicon_revision() >= 3) { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 7c209dc..3973f80 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -45,13 +45,13 @@
switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); return 256; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); return 128; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); return 64; }
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dece9bf..c86628b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1156,7 +1156,7 @@ sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) reg32 |= (1 << 7) | (1 << 5); else - reg32 |= (1 << 31); + reg32 |= (1U << 31);
/* Is channel 1 populated? */ if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || @@ -2006,7 +2006,7 @@
reg32 = MCHBAR32(WCC); reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + reg32 |= (4U << 29) | (3 << 25) | (1 << 10); MCHBAR32(WCC) = reg32;
MCHBAR32(SMVREFC) |= (1 << 6);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31408 )
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
Patch Set 1:
(6 comments)
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/acpi.c File src/northbridge/intel/i945/acpi.c:
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/acpi.c@44 PS1, Line 44: pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/acpi.c@48 PS1, Line 48: pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/acpi.c@52 PS1, Line 52: pciexbar = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/northbrid... File src/northbridge/intel/i945/northbridge.c:
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/northbrid... PS1, Line 48: *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/northbrid... PS1, Line 51: *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/1/src/northbridge/intel/i945/northbrid... PS1, Line 54: *base = pciexbar_reg & ((1U << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31408
to look at the new patch set (#2).
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
nb/intel/i945: Use big enough type for left-shift
Change-Id: I7eb5850e4af3d5a41973a73737751b0f29c9d507 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c 4 files changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31408/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31408 )
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/acpi.c File src/northbridge/intel/i945/acpi.c:
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/acpi.c@44 PS2, Line 44: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/acpi.c@48 PS2, Line 48: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/acpi.c@52 PS2, Line 52: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/northbrid... File src/northbridge/intel/i945/northbridge.c:
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/northbrid... PS2, Line 48: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/northbrid... PS2, Line 51: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/2/src/northbridge/intel/i945/northbrid... PS2, Line 54: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31408 )
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c File src/northbridge/intel/i945/acpi.c:
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@44 PS3, Line 44: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@48 PS3, Line 48: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@52 PS3, Line 52: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... File src/northbridge/intel/i945/northbridge.c:
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 48: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 51: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 54: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31408 )
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
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