Change in coreboot[master]: soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to ...

[Furquan Shaikh (Code Review)]

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Angel Pons, Michal Motyl, Andrey Petrov, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51767 )

Change subject: soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
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Patch Set 8: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51767/comment/a3c16e21_6d8a24cc 
PS8, Line 11: 2. An advanced GPIO PM capabilities has been introduced in CNP PCH.
This statement looks incomplete.

https://review.coreboot.org/c/coreboot/+/51767/comment/8dd0a8de_d828cb16 
PS8, Line 19: MISCCFG bit definitions from intelblock/gpio.h
            : to soc/gpio.h
bit definitions are kept in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support.